Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-17
2007-07-17
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S013000
Reexamination Certificate
active
11053078
ABSTRACT:
Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.
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Likovich, Jr. Robert Brian
Mendenhall Joseph David
Morris John Christopher
Reese Robert James
Winemiller Chad Everett
Cockburn Joscelyn G.
International Business Machines - Corporation
Schubert Osterrieder & Nickelson PLLC
Whitmore Stacy A
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