Methods, systems, and devices for providing an interrupt...

Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S049000, C211S010000

Reexamination Certificate

active

07668998

ABSTRACT:
In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus. Related systems and devices are also discussed, including the use of the primary and secondary interrupt request lines to provide bus arbitration between the plurality of slave nodes for communication with the master node.

REFERENCES:
patent: 4639859 (1987-01-01), Ott
patent: 4654820 (1987-03-01), Brahm et al.
patent: 5327121 (1994-07-01), Antles, II
patent: 5475846 (1995-12-01), Moore
patent: 5765000 (1998-06-01), Mitchell et al.
patent: 5787258 (1998-07-01), Costa et al.
patent: 6006946 (1999-12-01), Williams et al.
patent: 6036812 (2000-03-01), Williams et al.
patent: 6128691 (2000-10-01), Haren et al.
patent: 6141703 (2000-10-01), Ding et al.
patent: 6176392 (2001-01-01), William et al.
patent: 6263395 (2001-07-01), Ferguson et al.
patent: 6708241 (2004-03-01), Futral
patent: 6971541 (2005-12-01), Williams et al.
patent: 7014063 (2006-03-01), Shows et al.
patent: 7344049 (2008-03-01), Daniels et al.
patent: 2003/0149827 (2003-08-01), Smolen et al.
patent: 2005/0268016 (2005-12-01), Mowry et al.
patent: 2005/0283554 (2005-12-01), Davies et al.
patent: 2006/0241807 (2006-10-01), Daniels et al.
patent: 2007/0208820 (2007-09-01), Makhervaks et al.
patent: 2008/0110555 (2008-05-01), Bouchelle et al.
patent: 2008/0110921 (2008-05-01), DuMond et al.
patent: 2008/0168751 (2008-07-01), Sink et al.
patent: 2008/0169302 (2008-07-01), Young et al.
patent: 2008/0283179 (2008-11-01), Sink
patent: 2008/0283544 (2008-11-01), Daniels et al.
Vallius et al., “Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems”, 4thIEEE International Symposium on Electronics Design, Test and Applications, pp. 119-124 (Jan. 23, 2008) XP031234463.
International Search Report and Written Opinion (14 pages) corresponding to International Application No. PCT/US2008/014106; Mailing Date: May 28, 2009.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods, systems, and devices for providing an interrupt... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods, systems, and devices for providing an interrupt..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods, systems, and devices for providing an interrupt... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4151796

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.