Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
2008-08-05
2010-02-23
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S049000, C211S010000
Reexamination Certificate
active
07668998
ABSTRACT:
In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus. Related systems and devices are also discussed, including the use of the primary and secondary interrupt request lines to provide bus arbitration between the plurality of slave nodes for communication with the master node.
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International Search Report and Written Opinion (14 pages) corresponding to International Application No. PCT/US2008/014106; Mailing Date: May 28, 2009.
Perisich Mark
Uebel Mark Alan
Dang Khanh
Myers Bigel Sibley & Sajovec P.A.
Parata Systems, LLC
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