Methods of writing/erasing of nonvolatile semiconductor...

Details Methods of writing/erasing of nonvolatile semiconductor... Methods of writing/erasing of nonvolatile semiconductor...

2002-07-17

2004-07-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C365S185140, C365S185290

Reexamination Certificate

active

06767790

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, and especially to writing/erasing of memory cells in a flash memory.
2. Description of the Background Art
Of electrically rewritable nonvolatile semiconductor storage devices, flash memories capable of erasing the entire or a block of data by one operation are well known in the art. Such flash memories are disclosed for example in Japanese Patent Application Laid-open Nos. 2001-28428, 2001-85540, and 2001-85541.
FIGS. 6
to
13
are cross-sectional views illustrating a method of manufacturing a group of memory transistors (memory cells) in a conventional flash memory. Referring to the drawings, the manufacturing procedure will be described hereinbelow.
Initially, as shown in
FIG. 6
, a silicon oxide film
102
is grown to a thickness of about 100 angstroms by thermal oxidation on the surface of a P-type silicon substrate
101
having a (001) crystal orientation, and then a phosphorus-doped polycrystalline silicon layer
103
is deposited by low-pressure CVD to a thickness of about 2000 angstroms. Following this, a silicon oxide film
104
is deposited to a thickness of about 1500 angstroms by low-pressure CVD.
After a predetermined pattern of resist (not shown) is formed by photolithography techniques, as shown in
FIG. 7
, the silicon oxide film
104
is etched using the resist as a mask, thereby to obtain a patterned silicon oxide film
104
a
. Using the silicon oxide film
104
a
as a mask, the phosphorus-doped polycrystalline silicon layer
103
is patterned to form a plurality of floating gates
103
a.
Then, arsenic ions
111
are angularly implanted at an implant energy of 40 keV and a dose of 5×10
15
cm
2
as shown in
FIG. 8
, and the annealing is carried out in a nitrogen atmosphere, whereby N
+
diffusion regions
105
of memory transistors are formed. At this time, parts of the N
+
diffusion regions
105
are formed under the floating gates
103
a.
As shown in
FIG. 9
, exposed portions of the silicon oxide film
102
and the silicon oxide film
104
are removed by etching in a HF solution, so that only the silicon oxide film
102
directly below the floating gates
103
a
remain as silicon oxide films
102
r
. Further, a three-layer insulating film
106
, consisting of a silicon oxide film of about 50 angstroms thick, a silicon nitride film of about 100 angstroms thick, and a silicon oxide film of about 50 angstroms thick, is deposited over the whole surface by low-pressure CVD.
Following this, as shown in
FIG. 10
, a phosphorus-doped polycrystalline silicon layer
107
is deposited over the whole surface to a thickness of about 1000 angstroms by low-pressure CVD.
The phosphorus-doped polycrystalline silicon layer
107
is, as shown in
FIG. 11
, etched back so that only the portions thereof on the three-layer insulating film
106
where the floating gates
103
a
are not formed, remain as a plurality of access gates
107
a
. Thus the other parts of the N
+
diffusion regions
105
are located under the access gates
107
a
. That is, the N
+
diffusion regions
105
each are formed under one floating gate
103
a
and one access gate
107
a
to extend thereacross.
The surfaces of the access gates
107
a
are thermally oxidized to form a silicon oxide film
108
of about 300 angstroms thick, as shown in FIG.
12
.
Then, as shown in
FIG. 13
, a phosphorus-doped polycrystalline silicon layer
119
of about 2000 angstroms thick and a silicon oxide film
120
of about 2200 angstroms thick are successively deposited by low-pressure CVD.
After a predetermined pattern of resist (not shown) is formed on the silicon oxide film
120
by photolithography techniques, the silicon oxide film
120
is etched using the resist as a mask and the resist is removed. Further, the phosphorus-doped polycrystalline silicon
119
is etched using the silicon oxide film
120
as a mask, whereby a control gate
109
is formed.
FIG. 14
is a plan view illustrating a plan configuration after the formation of the control gate
109
. As shown, a plurality of lines of control gates
109
are formed, each extending from side to side.
FIG. 13
is the equivalent of a cross section of
FIG. 14
taken along the line A—A.
As illustrated in the cross-sectional view of FIG.
15
and the plan view of
FIG. 16
, the three-layer insulating film
106
formed on the floating gates
103
a
, and the floating gates
103
a
are removed by etching using the silicon oxide film
120
as a mask. Thereby the patterning of the floating gates
103
a
is completed and the silicon oxide film
120
is removed.
FIG. 16
is the equivalent of a cross section of
FIG. 15
taken along the line B—B.
In this fashion, one memory transistor is formed of the control gate
109
, a set of one floating gate
103
a
and one access gate
107
a
that are adjacent to each other with the three-layer insulating film
106
sandwiched in between, and a pair of N
+
diffusion regions
105
, parts of which are formed under the above set of one floating gate
103
a
and one access gate
107
a
. By forming a plurality of such memory transistors adjacent to one another, a group of memory transistors can be obtained.
Referring to
FIG. 13
, for example, one memory transistor MT(n) is formed of the control gate
109
, a floating gate
103
a
(
n
), an access gate
107
a
(
n
), and N
+
diffusion regions
105
(
n
) and
105
(
n
+1).
The plurality of N
+
diffusion regions
105
are configured such that their respective potentials can be set individually for reasons of necessity to perform a write operation for each memory transistor. The plurality of access gates
107
a
are configured such that at least adjacent access gates
107
a
can be set at different potentials for reasons of necessity to ensure normal write operations.
For instance, the plurality of access gates
107
a
are configured such that the potentials of a group of access gates {
107
a
(
n
−3),
107
a
(
n
−1),
107
a
(
n
+1), and
107
a
(
n
+3)} and a group of access gates {
107
a
(
n
−2),
107
a
(
n
), and
107
a
(
n
+2)} can be set on an individual basis.
In the flash memory with such a memory transistor structure, the contents of information to be stored in each memory transistor is determined according to whether the memory transistor has a high threshold voltage Vthp due to electron injection in its floating gate
103
a
or has a low threshold voltage Vthe due to electron emission from its floating gate
103
a.
A memory transistor that has a high threshold voltage Vthp due to electron injection in its floating gate
103
a
is regarded as being in a written state. Since electrons stored in the floating gate
103
a
will not be destroyed semi-permanently unless they are forcedly emitted for example by an erase operation, information stored therein is also semi-permanent. A memory transistor that has a low threshold voltage Vthe due to electron emission from its floating gate
103
a
, on the other hand, is regarded as being in an erased state.
By detecting the state of each memory transistor, either “written” or “eased”, information stored in the memory transistor (memory cell) can be read.
FIG. 17
is a cross-sectional view for explaining a write operation on memory cells in a conventional flash memory. Referring to the drawing, the write operation on the memory cells will be described hereinbelow.
For convenience of explanation, the plurality of floating gates
103
a
are designated by
103
a
(
n
−3) to
103
a
(
n
+3), the plurality of N
+
diffusion regions
105
by
105
(
n
−3) to
105
(
n
+3), and the plurality of access gates
107
a
by
107
a
(
n
−4) to
107
a
(
n
+3) (the same applies to FIG.
18
).
The n-th memory transitory MT(n) is formed of the control gate
109
, the floating gate
103
a
(
n
), the access gate
107
a
(
n
), and the N
+
diffusion regions
105
(
n
) and
105
(
n
+1).
In this

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