Methods of vertically stacking wafers using porous silicon

Details Methods of vertically stacking wafers using porous silicon Methods of vertically stacking wafers using porous silicon

2008-05-27

2008-05-27

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Subsequent separation into plural bodies

C438S455000, C438S478000, C438S507000, C257SE27137, C257SE27144, C257SE27161

Reexamination Certificate

active

07378331

ABSTRACT:
A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

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