Methods of testing a digital frequency synthesizer in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S725000

Reexamination Certificate

active

10977565

ABSTRACT:
Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.

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patent: 6556044 (2003-04-01), Langhammer et al.
patent: 2003/0119466 (2003-06-01), Goldman
Niewiadomski, S., Building a frequency synthesizer in an FPGA, Sep. 1998, IML Techpress, Electronic Product Design, vol. 19, No. 9, p. C32, C34, C37-8.
Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 33-75 and 168-171.

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