Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-03-05
2004-12-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000
Reexamination Certificate
active
06836864
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to testing Programmable Logic Devices (PLDs). More particularly, the invention relates to methods for efficiently testing digital frequency synthesizer circuits included in the PLDs.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
Some FPGAs also include additional logic blocks with special purposes. For example, the Xilinx Virtex®-II FPGA includes blocks of Random Access Memory (RAM) and blocks implementing multiplier functions. (The Xilinx Virtex-II FPGA is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
Another special-purpose logic block included in the Virtex-II FPGA is a Digital Frequency Synthesizer (DFS) circuit. This circuit is described in pages 66 and 168-171 of the “Virtex-II Platform FPGA Handbook”, which pages are incorporated herein by reference.
The Virtex-II DFS circuit allows a multiplier (M) and a divider (D) to be applied to a first clock signal having a given input frequency to derive a second clock signal having a desired output frequency. The range of M is 1-4096, while the range of D is also 1-4096. Therefore, the maximum number of all M/D (M divided by D) combinations is 4096×4096=16,777,216.
Thus, to fully test the Virtex-II DFS circuit using conventional test methods would require that 16,777,216 different configuration data files (bitstreams) be created and stored, with each bitstream then being downloaded to each manufactured device and tested in operation in each device. Clearly, such a test procedure is prohibitively time-consuming. In fact, simply storing the bitstreams needed for such a test procedure would be quite impractical, as would providing the computer time necessary to generate the bitstreams and to test each manufactured device with each bitstream.
Therefore, it is desirable to provide methods for maximizing test coverage of a DFS circuit in a PLD without loading and testing every possible combination of M and D.
SUMMARY OF THE INVENTION
The invention provides methods of testing a digital frequency synthesizer (DFS) circuit in a programmable logic device (PLD), and of generating configuration data files for testing a DFS circuit in a PLD. The DFS circuit provides a programmable multiplier M and a programmable divider D. The methods of the invention reduce both test time and memory storage requirements by reducing an exhaustive set of tests (wherein every value of M and D is tested) to a smaller set of tests in which each M/D ratio is tested to a specified resolution.
According to a first embodiment of the invention, minimum and maximum values are specified for M, D, and M/D. The specified values define an “MD area” that includes all of the MD pairs for which M, D, and M/D fall within ranges defined by the specified minimum and maximum values. A resolution for testing the DFS circuit is also specified. A memory array is then allocated, the array having a size determined by the allowed range of M/D and the specified resolution. Thus, each M/D ratio has a corresponding location in the array, up to the specified resolution.
An MD pair is then selected from the MD area. The M/D ratio is calculated for the MD pair, then idealized (e.g, rounded off) based on the specified resolution. The MD pair is then stored in the array location specified by the idealized M/D ratio. In one embodiment, the MD pair is only stored in the array if no other MD pair has already been stored in that location. In another embodiment, the MD pair overwrites the previous MD pair stored in the location. In other embodiments, the new MD pair and the previously stored MD pair are evaluated and one of the two pairs is retained based on the results of the evaluation. After storing (or selectively storing) the MD pair, another MD pair is selected, and the steps are repeated until each MD pair in the MD area has been processed.
The result of this process is an array of MD pairs that includes either zero or one MD pair for each idealized M/D ratio falling within the specified parameters. Thus, by testing each MD pair within the array, all allowable values of M/D are tested (i.e., all permissible permutations of the input clock frequency are generated), while performing only a subset of the full set of tests. Thus, both testing time and memory storage requirements for test configuration data files are significantly reduced.
In one embodiment, the time required to generate configuration data files is further reduced by using a template configuration data file that includes all configuration information for the PLD except for the programmable M and D values. The various configuration data files required for testing the various M/D ratios are generated by modifying the template configuration data file to include the corresponding M and D values stored in the array. In one embodiment, the template configuration data file includes default M and D values that are overwritten for each new M/D ratio (i.e., for each new configuration data file).
Using this technique, the modified configuration data files are generated so quickly and easily that there is no need to store the files. Each modified configuration data file is generated and transferred to the PLD under test “on the fly”. In another embodiment, only the current modified configuration data file is stored. In either case, the need for memory storage space is dramatically reduced over that required using conventional test methods.
Another aspect of the invention provides a method for generating configuration data files for testing programmable circuits in a PLD. In a first embodiment, an array is created that includes set of parameters for the programmable circuit. A template configuration data file is read that includes all configuration information for the PLD except for the parameter values. In one embodiment, the template configuration data file includes default parameter values that are overwritten for each new configuration data file.
After creating the array and reading the template configuration data file, a location in the array is selected that includes a stored set of parameters. The parameter values are read from the selected array location, then translated into bits of configuration data. A modified configuration data file is then generated using the template configuration data file and the bits of configuration data. The PLD is then configured using the modified configuration data file, and the programmable circuit is tested. This process can be repeated for each stored set of parameters in the array.
REFERENCES:
patent: 6202182 (2001-03-01), Abramovici et al.
patent: 6556044 (2003-04-01), Langhammer et al.
Niewiadomski, S., Building a frequency synthesizer in an FPGA, Sep. 1998, IML Techpress, Electronic Product Design, vol. 19, No. 9, p. C32, C34, C37-8.*
Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124; pp. 33-75 and 168-171.
Cartier Lois D.
De'cady Albert
Kerveros James
Xilinx , Inc.
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