Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-04-24
2010-11-23
Tran, Vincent T (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C327S065000, C327S175000, C327S354000, C327S355000
Reexamination Certificate
active
07840831
ABSTRACT:
Phase correction circuits and methods for reducing phase skew between multiphase clock signals and a semiconductor device including the circuit are provided. The semiconductor device includes a phase correction circuit and an output buffer. The phase correction circuit corrects phase skew between multiphase clock signals and generates skew-corrected clock signals. The output buffer outputs data in synchronization with the skew-corrected clock signals. The phase correction circuit includes a phase corrector, a replication output buffer, a phase detector, and a controller. The phase corrector corrects a duty cycle of a first clock signal, a duty cycle of a second clock signal, and phase skew between the first and second clock signals and generates skew-corrected first and second clock signals. The replication output buffer has the same structure as a data output buffer and outputs replication data in synchronization with the skew-corrected first and second clock signals. The phase detector detects a phase error in data output from the replication output buffer and generates a detection signal. The controller controls the phase corrector in response to the detection signal. Accordingly, phase skew between multiphase clock signals can be reduced or eliminated.
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Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tran Vincent T
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