Methods of providing electrical isolation in semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S197000, C438S142000, C257SE21540

Reexamination Certificate

active

07824983

ABSTRACT:
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffectiveand the field gate oxide. Semiconductor structures formed by these methods are also disclosed.

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patent: 2006/0258109 (2006-11-01), Juengling
patent: 2007/0134884 (2007-06-01), Kim et al.
patent: 2008/0121970 (2008-05-01), Aritome
International Search Report for International Application No. PCT/US2009/045417 mailed Jan. 14, 2010, 4 pages.
International Written Opinion for International Application No. PCT/US2009/045417 mailed Jan. 14, 2010, 8 pages.

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