Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-04
2003-12-30
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S627000, C438S653000
Reexamination Certificate
active
06670233
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electrode and barrier materials for semiconductor memory devices or thin film capacitors containing ferroelectric or high-epsilon dielectric materials and in particular, to a method for patterning a lower electrode including a noble metal and multilayer barrier films.
The increasing density of integrated circuits (e.g. DRAMs) is increasing the need for materials with high dielectric constants to be used in electrical devices such as capacitors. Generally, capacitance is directly related to the surface area of the electrode in contact with the capacitor dielectric, but is not significantly affected by the electrode volume. The current method generally utilized to achieve higher capacitance per unit area is to increase the surface area/unit area by increasing the topography, such as in trench and stack capacitors using SiO
2
or SiO
2
/Si
3
N
4
as the dielectric. This approach becomes very difficult in terms of manufacturability for devices such as the 256 Mbit and 1 Gbit DRAMs.
An alternative approach is to use materials having a high dielectric constant. Many perovskite, ferroelectric, or high dielectric constant materials such as (Ba,Sr)TiO
3
(BST) usually have much larger capacitance densities than standard SiO
2
—Si
3
N
4
—SiO
2
capacitors. Various metals and metallic compounds, and typically noble metals such as Pt and conductive oxides such as RuO
2
, have been proposed as the electrodes for these high dielectric constant materials. To be useful in electronic devices, however, reliable electrical connections should generally be constructed which do not diminish the beneficial properties of these high-dielectric-constant materials.
Multilayer barrier materials such as iridium oxide, iridium, tantalum silicon nitride, tantalum silicon and the like are being investigated for application in these high dielectric constant (BST) stacked capacitor memory cells. The multilayered barrier structures typically consist of two or more barrier materials. The barrier layer prevents interdiffusion between underlying devices and a lower electrode material formed with the noble metal.
Noble metals are chosen for the electrode because these metals are generally resistant and/or inert to oxidation. Precious metals such as platinum, palladium, etc. are typically used as the electrode material. Of these, platinum appears to be most preferred since it is inert to oxidation, has a low leakage current (<10
−9
amps/cm
2
) and exhibits high conductivity.
Etching multilayer film stacks including the barrier layers and electrode structures is difficult. Current processes are generally complex, and typically result in sloped sidewall profiles with significant amounts of etch residues remaining on the wafer. Moreover, current processes typically require multiple lithographic processing steps for patterning the barrier layer and then the electrode. For example, a prior art process may include the following steps: deposition of the barrier film stack onto a substrate, e.g., IrO
2
/Ir/TaSiN/TaSi, followed by photolithographic patterning. The multilayer barrier is then etched such as for example by a chlorine (Cl
2
) plasma. Since IrCl
2
is formed during the etching process, the wafer is then rinsed to removed the IrCl
2
residues. A dielectric interlayer is then deposited and further requires planarization to expose the IrO
2
surface of the multilayer barrier. The electrode, e.g., platinum, is then deposited which requires additional photolithographic processing. The electrode is etched and the mask is then removed to complete the multilayer film stack. The film stack after each patterning step are shown in the scanning electron microscopy photomicrographs of
FIGS. 1 and 2
.
FIG. 1
is a cross section after the barrier layer stack is conventionally patterned and
FIG. 2
shows the film stack after conventionally forming the electrode over the patterned barrier film stack. The process clearly results in poor profile angles, even after overetch conditions.
As described, the prior art typically requires numerous processing steps to first define the pattern in the multilayer barrier and then additional processing steps to define the pattern for the electrode. The numerous process steps to form the lower electrode of a capacitor significantly adds to the cost and complexity. The multiple process steps require rigid control of alignment and overlay. Moreover, cycle time is impacted as a result of the numerous process steps.
Accordingly there is a need for a simpler and more robust process for patterning multilayer film stacks containing a noble metal.
SUMMARY OF THE INVENTION
A method of forming a lower electrode of a capacitor. The method includes forming a barrier film on a semiconductor substrate. The barrier film includes one or more layers of a compound selected from the group consisting of titanium nitride, titanium silicate, titanium silicate nitride, titanium aluminum nitride, tantalum silicate and tantalum silicate nitride, iridium, iridium oxide and mixtures thereof. A conductive film containing a metal is formed on the barrier film. The conductive film includes one or more layers of a noble metal selected from the group consisting of platinum, palladium, gold, silver, ruthenium, osmium, rhenium, rhodium, iridium, oxides of these noble metals and alloys thereof. A patterned mask layer is formed on the conductive film, wherein the mask layer selectively exposes portions of the conducting film. A plasma etches the exposed portions of the conductive film to a surface of the semiconductor substrate, wherein the plasma removes the exposed portions of the conductive film and respective portions of the underlying barrier film. The plasma is formed from an excitable gas mixture essentially free from a hydrogen bearing gas. The hydrogen free excitable gas mixture includes argon gas, a chlorine bearing gas, a carbon bearing gas and a fluorine bearing gas.
A process for removing exposed portions of a multilayer film stack from a substrate wherein the multilayer film stack inlcudes a noble metal layer and one or more barrier layers. The process includes reacting the exposed portions of the multilayer film stack with reactive species for a period of time effective to substantially remove the film stack from the substrate. The reactive species are essentially free from hydrogen species and are generated by exposing an excitable gas mixture to an energy source sufficient to generate the reactive species. The gas mixture includes argon, a chlorine bearing compound, a carbon bearing compound and a fluorine bearing compound.
Other embodiments of the invention are contemplated to provide particular features and structural variants of the basic elements. The specific embodiments referred to as well as possible variations and the various features and advantages of the invention will become better understood when considered in connection with the detailed description and drawings that follow.
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Athavale Satish D.
Costrini Greg
Cantor & Colburn LLP
Capella Steven
Dang Phuc T.
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