Methods of manufacturing a stressed MOS transistor structure

Details Methods of manufacturing a stressed MOS transistor structure Methods of manufacturing a stressed MOS transistor structure

2008-03-04

2008-03-04

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000

Reexamination Certificate

active

07338847

ABSTRACT:
An intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure. A layer is created on a surface of the recess to induce an appropriate type of stress in the channel.

REFERENCES:
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6399973 (2002-06-01), Roberds
patent: 6515338 (2003-02-01), Inumiya et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6580134 (2003-06-01), Song et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6717213 (2004-04-01), Doyle et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6982465 (2006-01-01), Kumagai et al.
patent: 7190036 (2007-03-01), Ko et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2003/0111699 (2003-06-01), Wasshuber et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
Shimizu, A. et al.,Local Mechanical-Stress Control(LMC): A New Technique for CMOS-Performance Enhancement, Hitachi ULSI Systems, Co., Ltd., Tokyo, Japan (2001).
Ito, Shinya et al.,Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design, ULSI Device Development Div., NEC Corp. (2000).

Affiliated with

Also associated with

Rating

Methods of manufacturing a stressed MOS transistor structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of manufacturing a stressed MOS transistor structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of manufacturing a stressed MOS transistor structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2807804