Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-08
2008-07-08
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000, C438S427000, C257SE21546, C257SE21549, C257SE21573
Reexamination Certificate
active
07396728
ABSTRACT:
A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
REFERENCES:
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6642125 (2003-11-01), Oh et al.
patent: 6900502 (2005-05-01), Ge et al.
patent: 2002/0031890 (2002-03-01), Watanabe et al.
Holt Jonathan McAulay
Mehta Narendra Singh
Varghese Ajith
Brady III Wade J.
Lindsay, Jr. Walter L
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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