Methods of forming vertical transistors

Details Methods of forming vertical transistors Methods of forming vertical transistors

2006-09-14

2008-08-12

Pham, Thanh Van (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S206000, C438S209000, C438S036000, C257SE21375, C257SE21410, C257SE21629

Reexamination Certificate

active

07410856

ABSTRACT:
A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.

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