Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-17
2004-07-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000
Reexamination Certificate
active
06764889
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor switching devices, and more particularly to switching devices for high power applications and methods of forming same.
BACKGROUND OF THE INVENTION
The silicon bipolar transistor has been the device of choice for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm
2
and support relatively high blocking voltages in the range of 500-1000V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices that require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications that also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement mode MOSFET occurs when a conductive N-type inversion layer channel is formed in the P-type base region (also referred to as “channel region”) in response to the application of a positive gate bias. The inversion layer channel electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET's gate electrode is separated from the base region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the base region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's base region. Thus, only charging and discharging current (“displacement current”) is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination and storage of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as “second breakdown”. Power MOSFETs can also be easily paralleled, because the forward voltage drop across power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
In view of these desirable characteristics, many variations of power MOSFETs have been designed. Two popular types are the double-diffused MOSFET device (DMOSFET) and the UMOSFET device. These and other power MOSFETs are described in a textbook by B. J. Baliga entitled
Power Semiconductor Devices
, PWS Publishing Co. (ISBN 0-534-94098-6) (1995), the disclosure of which is hereby incorporated herein by reference. Chapter 7 of this textbook describes power MOSFETs at pages 335-425. Examples of silicon power MOSFETs including accumulation, inversion and extended trench FETs having trench gate electrodes extending into an N+ drain region are also disclosed in an article by T. Syau, P. Venkatraman and B. J. Baliga, entitled
Comparison of Ultralow Specific On
-
Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFETs
, IEEE Transactions on Electron Devices, Vol. 41, No. 5, May (1994). As described by Syau et al., specific on-resistances in the range of 100-250 &mgr;&OHgr;cm
2
were experimentally demonstrated for devices capable of supporting a maximum of 25 volts. However, the performance of these devices was limited by the fact that the forward blocking voltage must be supported across the gate oxide at the bottom of the trench.
FIG. 1
, which is a reproduction of FIG.
1
(
d
) from the aforementioned Syau et al. article, discloses a conventional UMOSFET structure. In the blocking mode of operation, this UMOSFET supports most of the forward blocking voltage across the N-type drift layer that must be doped at relatively low levels to obtain a high maximum blocking voltage capability, however low doping levels typically increase the on-state series resistance. Based on these competing design requirements of high blocking voltage and low on-state resistance, a fundamental figure-of-merit for power devices has been derived that relates specific on-resistance (R
on,sp
) to the maximum blocking voltage (BV). As explained at page 373 of the aforementioned textbook to B. J. Baliga, the ideal specific on-resistance for an N-type silicon drift region is given by the following relation:
R
on,sp
=5.93×10
−9
(
BV
)
2.5
(1)
Thus, for a device with 60 volt blocking capability, the ideal specific on-resistance is 170 &mgr;&OHgr;cm
2
. However, because of the additional resistance contribution from the base region (e.g., P-type base region in an N-channel MOSFET), reported specific on-resistances for UMOSFETs are typically much higher. For example, a UMOSFET having a specific on-resistance of 730 &mgr;&OHgr;cm
2
is disclosed in an article by H. Chang, entitled
Numerical and Experimental Comparison of
60
V Vertical Double
-
Diffused MOSFETs and MOSFETs With A Trench
-
Gate Structure
, Solid-State Electronics, Vol. 32, No. 3, pp. 247-251 (1989). However, in this device, a lower-than-ideal uniform doping concentration in the drift region was required to compensate for the high concentration of field lines near the bottom corner of the trench when blocking high forward voltages. U.S. Pat. Nos. 5,637,989, 5,742,076 and 5,912,497, the disclosures of which are hereby incorporated herein be reference, also disclose popular power semiconductor devices having vertical current carrying capability.
In particular, U.S. Pat. No. 5,637,898 to Baliga discloses a preferred silicon field effect transistor that is commonly referred to as a graded-doped (GD) UMOSFET. As illustrated by
FIG. 2
, which is a reproduction of
FIG. 3
from the '898 patent, a unit cell
100
of an integrated power semiconductor device field effect transistor may have a width “W
c
” of 1 &mgr;m and comprise a highly doped drain layer
114
of first conductivity type (e.g., N+) substrate, a drift layer
112
of first conductivity type having a linearly graded doping concentration therein, a relatively thin base layer
116
of second conductivity type (e.g., P-type) and a highly doped source layer
118
of first conductivity type (e.g., N+). The drift layer
112
may be formed by epitaxially growing an N-type in-situ doped monocrystalline silicon layer having a thickness of 4 &mgr;m on an N-type drain layer
114
having a thickness of 100 &mgr;m and a doping concentration of greater than 1×10
18
cm
−3
(e.g. 1×10
19
cm
−3
) therein. The drift layer
Elms Richard
Myers Bigel & Sibley & Sajovec
Owens Beth E.
Silicon Semiconductor Corporation
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