Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-07-13
2002-10-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S778000, C438S787000, C438S585000, C438S522000, C438S473000
Reexamination Certificate
active
06458717
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of forming semiconductor devices and specifically to methods of forming ultra-thin buffer oxide layers below the gate dielectric in semiconductor device fabrication.
BACKGROUND OF THE INVENTION
Many current processes for forming the thin buffer oxide layer below the SiN (silicon nitride) gate dielectric involves either a furnace or Rapid Thermal Oxidation (RTO). Other methods involve an extremely dilute HF oxide etch back from a thicker grown oxide (SiO).
It is extremely difficult to grow an oxide thickness of less than 10 Å with the traditional furnace oxidation. Even with RTO oxidation, controlling the oxide thickness is an issue for thicknesses less than 10 Å. With the oxide etch back process using extremely dilute HF, i.e. >100:1, control and uniformity is also difficult to maintain.
U.S. Pat. No. 5,963,818 to Kao et al. describes a method for forming an integrated circuit involves forming trench isolation regions and a damascene gate electrode region simultaneous with one another by over-lapping process steps using, inter alia, an inverse poly gate CMP.
U.S. Pat. No. 5,960,270 to Misra et al. describes a method for forming a metal gate MOS transistor using an inverse poly gate CMP. Source and drain regions are formed within a substrate self-aligned to a lithographically patterned feature. The patterned feature is then removed and replaced by a metallic gate layer that is chemically mechanically polished (CMP) to form a metallic plug region that is either an inlaid or dual inlaid. The metallic plug region is self-aligned to the source and drain regions and preferably functions as a metal MOS gate region.
U.S. Pat. No. 5,943,576 to Kapoor describes a method of forming a MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,899,719 to Hong describes a method for making an FET (field effect transistor) having narrower gate electrodes and forming source/drain regions, including halo implants, in a more controlled manner. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,872,038 to Duane et al. describes a process for forming a semiconductor device having an elevated active region. A plurality of gate electrodes is formed on the semiconductor substrate an a thick oxide layer is disposed over the gate electrodes. A trench is formed in the thick oxide layer and is filled with a polysilicon material that is later doped to form an elevated active region above an active region of the substrate. The process includes a plain inverse poly gate CMP process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming an extremely thin (3-10 Å) buffer oxide layer.
Another object of the present invention is to provide a method of forming buffer oxide layers for SiN gate dielectrics by accurate control of the oxygen implant dose to permit formation of ultra thin (3-10 Å) buffer oxide layers.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, the first option is a method of forming an ultra thin buffer oxide layer comprising the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer.
The second option is a method of forming an ultra-thin buffer oxide layer, comprising the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A gate dielectric layer is formed over the silicon substrate and the STI regions. A sacrificial oxide layer is formed over the gate dielectric layer. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer.
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Lee James Yong Meng
Li Xia
Zhang Yunqzang
Chartered Semiconductor Manufacturing Ltd.
Lee, Jr. Granvill D.
Pike Rosemary L. S.
Smith Matthew
Stanton Stephen G.
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