Methods of forming transistors

Details Methods of forming transistors Methods of forming transistors

2000-08-09

2002-01-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S289000, C438S291000, C257S412000, C257S413000

Reexamination Certificate

active

06335254

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming transistors and semiconductor processing methods of forming transistor gates.
BACKGROUND OF THE INVENTION
Conductive runners are a fundamental link for components of an integrated circuit for transmitting information. One conventional construction for a conductive runner, for example, a gate line or word line, includes a silicide layer over a silicon layer such as polysilicon. The elecrical resistance of such a construction has become a problem as the semiconductor industry continually strives to decrease the size of components in an integrated circuit. Accordingly, there is a desire in the industry to construct conductive runners with higher conductivity characteristics.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer.
In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate.
In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.
In still yet another aspect of the invention, a method to form a transistor includes sequentially forming a gate dielectric layer, a first conductive layer, and a sacrificial layer over a semiconductor substrate. The gate dielectric layer, the first conductive layer, and the sacrificial layer are patterned into a transistor gate stack. Insulative sidewall spacers are formed over sidewalls of the gate stack. The sacrificial layer is substantially removed from the gate stack between the spacers. After removing the sacrificial layer, a conductive material is formed between the spacers in electrical connection with the first conductive layer.


REFERENCES:
patent: 5497017 (1996-03-01), Gonzales
patent: 5583067 (1996-12-01), Sanchez
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5874328 (1999-02-01), Liu et al.
patent: 5949105 (1999-09-01), Moslehi
patent: 6140688 (2000-10-01), Gardner et al.

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