Methods of forming SRAM devices having buried layer patterns

Details Methods of forming SRAM devices having buried layer patterns Methods of forming SRAM devices having buried layer patterns

2010-01-14

2011-11-01

Coleman, William D (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S142000, C438S478000, C438S586000, C438S618000, C257S067000, C257S315000, C257S365000, C257S347000, C257SE21614, C257SE25018, C257SE27026, C257SE27064

Reexamination Certificate

active

08048727

ABSTRACT:
An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

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