Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-16
2001-07-10
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S491000
Reexamination Certificate
active
06258664
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming silicon-comprising materials having roughened outer surfaces. In particular aspects, the invention pertains to methods of forming capacitor constructions.
BACKGROUND OF THE INVENTION
It is frequently desirable to form semiconductive materials having roughened outer surfaces. An exemplary semiconductive material with a roughened outer surface is hemispherical grain (HSG) polycrystalline silicon. Such material is utilized in constructions wherein it is desirable to have an extensive surface area. An exemplary construction is a capacitor electrode. Specifically, one way of increasing the total charge that can be stored by a capacitor without increasing the wafer real estate consumed by the capacitor is to increase the surface area of the capacitor's electrodes.
A difficulty in forming hemispherical grain polysilicon is in controlling a rate and amount of growth of the hemispherical grains. Problems associated with poor control of grain growth are (1) too little grain growth produces less than a desired available surface area; (2) too large of grains formed within a container capacitor can overfill the container; and (3) too much grain growth on outer surfaces of adjacent capacitors can lead to shorting between the capacitors. In light of such difficulties, it would be advantageous to develop new methods of forming semiconductive materials having roughened outer surfaces. Particularly, it would be advantageous to develop new methods of forming polycrystalline silicon materials having roughened outer surfaces.
SUMMARY OF THE INVENTION
In one aspect, the invention includes a method of forming a silicon-comprising material having a roughened outer surface. A semiconductive substrate is provided. The substrate comprises conductively doped silicon. A layer is formed over the substrate. The layer comprises crystalline grains which include silicon and germanium, and has a surface exposed to a surrounding atmosphere. The layer is exposed to conditions which cause the crystalline grains to increase in size until roughness of the surface of the layer is increased. The layer with increased surface roughness and the substrate together define a silicon-comprising material having a roughened outer surface. Dopant is out-diffused from the conductively doped silicon and into the crystalline grains of the layer to conductively dope the layer.
In another aspect, the invention includes a method of forming a capacitor construction. A substrate is provided and a conductively doped silicon-comprising material is formed to be supported by the substrate. A layer is formed against the conductively doped silicon-comprising material. The layer has an outermost surface, and comprises silicon and germanium. The layer is subjected to conditions which increase a roughness of the outermost surface. The layer and the conductively doped silicon-comprising material together define a first capacitor electrode. Dopant is out-diffused from the conductively doped silicon-comprising material and into the layer. A dielectric layer is formed against said outermost surface. A second capacitor electrode is formed to be separated from the first capacitor electrode by the dielectric layer.
REFERENCES:
patent: 4891329 (1990-01-01), Reisman et al.
patent: 5166084 (1992-11-01), Pfiester
patent: 5218213 (1993-06-01), Gaul et al.
patent: 5240876 (1993-08-01), Gaul et al.
patent: 5246886 (1993-09-01), Sakai et al.
patent: 5658381 (1997-08-01), Thakur et al.
patent: 5665981 (1997-09-01), Banerjee et al.
patent: 5770500 (1998-06-01), Batra et al.
patent: 1-120069 (1989-05-01), None
patent: 4-168769 (1992-06-01), None
patent: 4-271126 (1992-09-01), None
patent: 4-313242 (1992-11-01), None
patent: 5-094929 (1993-04-01), None
patent: 5-94929 (1993-04-01), None
patent: 5-129635 (1993-05-01), None
patent: 5-175538 (1993-08-01), None
Yonehara, et al., “Abnormal Grain Growth In Ultra-Thin Films of Germanium on Insulator”,Mat. Res. Soc. Symp. Proc.,vol. 25, pp. 517-524, 1984.
Lee, et al., “Characteristic Comparison Between Ge-On-Insulator (GOI) and Si-On-Insulator (SOI) Beam-Induced Crystallization Mechanism,”Mat. Res. Soc. Symp. Proc.,vol. 74, pp. 577-583, 1987.
Hinckley, et al., “Charged Carrier Transport in Si1-xGexPseudomorphic Alloys Matched to Si-Strain Related Transport Improvements,”Appl. Phys. Lett.,vol. 55, pp. 2008-2010, Nov., 1989.
Kesan, et al., “High Performance 0.25 um p-MOSFETs With Silicon-Germanium Channels for 300K and 77K Operations,”IDEM Tech. Dig.,pp. 25-58, 1991.
Nayak, et al., “Enhancement-Mode Quantum-Well GexSi1-xPMOS,”IEEE Electron Device Letters,vol. 12, No. 4, pp. 154-156, Apr., 1991.
Nayak, et al., “High Performance GeSi Quantum-Well PMOS On SIMOX,”IEDM Tech. Dig.,pp. 777-780 , 1992.
Kuo, et al., “Modeling The Effect of Back Gate Bias On The Subthreshold Behavior Of A SiGe-Channel SOI PMOS Device,”Solid-State Electronics,vol. 36, No. 12, pp. 1757-61, Great Britain, Dec. 1993.
Bowers Charles
Hawranek Scott
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
LandOfFree
Methods of forming silicon-comprising materials having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming silicon-comprising materials having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming silicon-comprising materials having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558026