Methods of forming silicide layers on source/drain regions...

Details Methods of forming silicide layers on source/drain regions... Methods of forming silicide layers on source/drain regions...

2007-05-01

2007-05-01

Tran, Minh-Loan (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S683000, C438S303000, C438S305000, C257SE21438

Reexamination Certificate

active

10388354

ABSTRACT:
Methods of forming MOS transistors include forming lightly and heavily doped source/drain regions adjacent to one another in a substrate and a gate electrode with a sidewall spacer thereon. A salicide process is performed on a surface of the heavily doped source/drain region to provide a first suicide layer self-aligned to the sidewall spacer. At least a portion of the sidewall spacer is removed to expose a portion of the lightly doped source/drain region adjacent to the first silicide layer. A salicide process in performed on the exposed portion of the lightly doped source/drain region to provide a second silicide layer adjacent to the first suicide layer. Related devices are also disclosed.

REFERENCES:
patent: 4873557 (1989-10-01), Kita
patent: 6063681 (2000-05-01), Son
patent: 6084280 (2000-07-01), Gardner et al.
patent: 6124621 (2000-09-01), Lin et al.
patent: 6451693 (2002-09-01), Woo et al.
patent: 1998-029362 (1998-07-01), None
patent: 1999-0065455 (1999-08-01), None
Notice to File a Response/Amendment to the Examination Report (Korean & English Translation) dated Mar. 31, 2004.

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