Methods of forming self-aligned contact pads using a...

Details Methods of forming self-aligned contact pads using a... Methods of forming self-aligned contact pads using a...

2001-03-09

2003-09-02

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S183000, C438S176000, C438S180000, C438S181000, C438S184000, C438S185000, C438S269000, C438S275000, C438S587000

Reexamination Certificate

active

06613621

ABSTRACT:

This application claims priority to Korean Patent Application No. 2000-11821, filed on Mar. 9, 2000, and to No. 2000-55794, filed on Sep. 22, 2000, the contents of which are hereby incorporated herein by reference in their entireties.
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing, and more particularly to methods of forming self-aligned contacts.
BACKGROUND OF THE INVENTION
The semiconductor industry is continually striving to improve device performance while maintaining, or decreasing, the cost of the semiconductor product. These objects have been partially satisfied by the ability of the industry to create smaller semiconductor devices (or chips), thus enabling more semiconductor chips to be realized from a starting substrate, thus reducing the processing cost for a specific semiconductor chip. The ability to fabricate devices with sub-micron features has been the main contribution in obtaining smaller chips, with the smaller chips still maintaining levels of integration equal to integration levels achieved by larger chips.
The use of sub-micron features, or micro miniaturization, has resulted in smaller dimension of a gate electrode constituting a transistor. For example, feature sizes of about 0.1 microns may be realized. However, such micro-miniaturization may give rise to some problems in conventional gate electrode process. Particularly, micro-miniaturization may not ensure the reliability of the gate insulating layer.
A conventional gate electrode process is described as follows. A device isolation region is formed on a semiconductor substrate and impurities are implanted to form a channel region. A gate oxide layer and a gate electrode layer, such as polysilicon/tungsten layer, are sequentially formed and patterned into a gate electrode. Using the gate electrode as an implanting mask, impurities are implanted into the substrate to form low concentration drain regions, namely, LDD (lightly doped drain) regions.
The gate oxide may be subject to plasma damage during gate electrode patterning. In addition, the impurities implantation for the channel may degrade the reliability of the gate oxide. Furthermore, since channel impurities implantation is followed by LDD impurities implantation, impurities in the channel region may be re-distributed during an annealing process for curing point defects caused by the LDD impurities implantation.
In order to overcome some of the above-mentioned problems, a dummy gate process (or “damascene gate process”) has been developed.
FIGS. 1A
,
1
B and
2
are cross-sectional views of a semiconductor substrate to illustrate some problems associated with conventional dummy gate processes.
Referring to
FIGS. 1A and 1B
, a conventional dummy gate process is described. Referring now to
FIG. 1A
, a device isolation region
12
is formed in a predetermined portion of a semiconductor substrate
10
. A dummy gate pattern (not shown) can be formed thereon. Using the dummy gate pattern as a mask, LDD impurities implantation can be carried out and annealed to form LDD region
16
. A spacer
18
can be formed on a sidewall of the dummy gate pattern. A first insulating layer can be formed over an entire surface of the semiconductor substrate
10
and planarized down to a top surface of the dummy gate pattern to form a planarized first insulating layer
20
. The dummy gate pattern can then be selectively removed to form a groove. Through the groove, impurities are implanted to form a channel region (not shown).
In turn, a gate electrode material can be deposited in the groove and on the first insulating layer
20
, and then the gate electrode material can be planarized until the first insulating layer
20
is exposed, to form a gate electrode
24
. Subsequently, a bit line and a storage node contact process can be carried out for electrical connection to the LDD region
16
outside of the gate electrode
24
.
As is well known in the art, in order to provide process margin, a self-aligned contact process may be used during the bit line and storage node contact process. The self-aligned contact process selectively etches the oxide layer with respect to nitride layer covering the gate electrode, to form an opening exposing an LDD region. Accordingly, even in the presence of misalignment, the nitride layer protects the gate electrode, thereby blocking the gate electrode being exposed by the opening.
However, the conventional dummy gate process may suffer from problems during bit line and storage node contact formation processes. As shown in
FIGS. 1A and 1B
, the top of the gate electrode
24
may be exposed. Accordingly, the gate electrode
24
can be exposed when misalignment occurs during a photolithographic process used to form the contact. Namely, for a contact formation process, a second insulating layer
26
can be formed on the gate electrode
24
and on the first insulating layer
20
. Through a photo-etching process, the second and first insulating layers
26
and
20
are selectively etched with respect to the nitride sidewall spacer
18
, to form contact opening
28
a
and
28
b.
As can be seen, in the presence of the misalignment, the top of the gate electrode
24
can be exposed by the opening
28
a
and
28
b,
since the top of the gate is not protected. In addition, if the composition of the etchant is not optimal, the exposed gate electrode
24
may be etched. As a result, subsequently formed contact pads may come in contact with the gate electrode
24
.
Accordingly, a protection nitride layer may be formed only on the gate electrode
24
. However, it may be difficult to selectively form the protection nitride layer only on the gate electrode
24
. As can be seen in
FIG. 2
, the protection nitride layer
25
can be formed on the first insulating layer
20
and the gate electrode
24
. Accordingly, the protection nitride as well as the first and second insulating layers
20
and
26
is to be etched to form a contact opening, thereby making a self-aligned contact process difficult to achieve.
SUMMARY OF THE INVENTION
Embodiments according to the present invention can provide methods for forming self aligned contacts in integrated circuits. Pursuant to these embodiments, an insulating layer can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.
In some embodiments, the act of forming an insulating layer can be preceded by forming a dummy gate on the integrated circuit substrate including a spacer on a side wall of the dummy gate. In some embodiments, the act of forming the insulating later can be followed by removing the dummy gate and then forming a gate oxide layer in the groove.
In some embodiments, the act of removing can include dry etching the dummy gate and then wet etching the dummy gate. In some embodiments, the act of forming the conductive material in the groove can include the forming the conductive material in the groove recessed from an opening of the groove and on the insulating layer and removing the conductive material from the insulating layer and leaving conductive material in the groove.
In some embodiments, the act of removing the conductive material from the insulating layer and leaving conductive material in the groove can include forming an etching stopper layer on the conductive material in the groove and on the insulating layer and etching the etching stopper layer until the insulating layer is exposed.
In some embodiments the act of forming the conductive material in the groove can include forming the conductive material in the groove and on the insulating layer and etching the conductive material to recess the conductive material into the groove. In some embodiments, the act of etching the conduct

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