Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-11-14
1998-03-17
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438626, 438631, H01L 214763
Patent
active
057286272
ABSTRACT:
A conductive planarization layer, preferably a doped polysilicon layer, is used as a planarization layer for forming a conductive interconnect, such as a memory device bit line, thereon. Etching of the doped polysilicon planarization layer may be accurately controlled to form a planarized layer of controlled thickness, without requiring high temperature reflow heating of boro-phospo-silicate glass which can degrade transistor parameters. In particular, an insulating layer is formed on spaced apart source and drain regions and on the gate therebetween. A doped polysilicon layer is formed on the insulating layer. The doped polysilicon layer is planarized. A contact hole is formed in the insulating layer and in the doped polysilicon layer, to thereby expose the source or drain region. A conductive interconnect is then formed in the contact hole and on the gate.
REFERENCES:
patent: 4645562 (1987-02-01), Liao et al.
patent: 5346844 (1994-09-01), Cho et al.
patent: 5387533 (1995-02-01), Kim
Lee Won-seong
Nam In-ho
Chang Joni Y.
Niebling John
Samsung Electronics Co,. Ltd.
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