Semiconductor device manufacturing: process – Having organic semiconductive component
Reexamination Certificate
2002-12-05
2004-08-10
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Having organic semiconductive component
C257S040000
Reexamination Certificate
active
06773954
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to forming passive layers in organic memory cells. In particular, the present invention relates to efficient methods of forming passive layers thereby facilitating the function of an organic semiconductor memory cells.
BACKGROUND ART
The basic functions of a computer and memory devices include information processing and storage. In typical computer systems, these arithmetic, logic, and memory operations are performed by devices that are capable of reversibly switching between two states often referred to as “0” and “1.” Such switching devices are fabricated from semiconducting devices that perform these various functions and are capable of switching between two states at high speed.
Electronic addressing or logic devices, for instance for storage or processing of data, are made with inorganic solid state technology, and particularly crystalline silicon devices. The metal oxide semiconductor field effect transistor (MOSFET) is one the main workhorses.
Much of the progress in making computers and memory devices faster, smaller and cheaper involves integration, squeezing ever more transistors and other electronic structures onto a postage-stamp-sized piece of silicon. A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits.
Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The circuitry of volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity.
Moreover, as inorganic solid state device sizes decrease and integration increases, sensitivity to alignment tolerances increases making fabrication markedly more difficult. Formation of features at small minimum sizes does not imply that the minimum size can be used for fabrication of working circuits. It is necessary to have alignment tolerances which are much smaller than the small minimum size, for example, one quarter the minimum size.
Scaling inorganic solid stale devices raises issues with dopant diffusion lengths. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In this connection, many accommodations are made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely.
Applying a voltage across a semiconductor junction (in the reverse-bias direction) creates a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, punch-through or uncontrolled current flow, may occur.
Higher doping levels tend to minimize the separations required to prevent punch-through. However, if the voltage change per unit distance is large, further difficulties are created in that a large voltage change per unit distance implies that the magnitude of the electric field is large An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a hot electron, and may be sufficiently energetic to pass through an insulator, leading to irreversibly degradation of a semiconductor device.
Scaling and integration makes isolation in a monolithic semiconductor substrate more challenging. In particular, lateral isolation of devices from each other is difficult in some situations. Another difficulty is leakage current scaling. Yet another difficulty is presented by the diffusion of carriers within the substrate; that is free carriers can diffuse over many tens of microns and neutralize a stored charge.
SUMMARY OF THE INVENTION
The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides organic memory devices that possess one or more of the following: small size compared to inorganic memory devices, capability to store multiple bits of information, short resistance/impedance switch time, low operating voltages, low cost, high reliability, long life (thousands/millions of cycles), capable of three dimensional packing, associated low temperature processing, light weight, high density/integration, and extended memory retention.
One aspect of the present invention relates to a method of making an organic memory cell by providing a first electrode material in memory cell wells; removing a portion of the first electrode material to form first electrodes in the wells; depositing a passive layer material over the substrate; chemical mechanical polishing the passive layer material to form a passive layer in the well; forming an organic semiconductor layer over the passive layer; and providing a second electrode over the organic semiconductor layer.
Another aspect of the present invention relates to a method of making an organic memory cell by providing a first electrode material in memory cell wells; removing a portion of the first electrode material to form first electrodes in the wells; forming a passive layer over(the first electrodes in the wells; forming an organic semiconductor layer over the passive layer; and providing a second electrode over the organic semiconductor layer.
Yet another aspect of the present invention relates to a method of making an organic memory cell by forming a passive layer comprising a conductivity facilitating compound over a first electrode in a substrate; patterning a mask over the substrate, so that the mask is positioned over the first electrode thereby leaving exposed portions of the passive layer; removing the exposed portions of the passive layer; removing the mask; forming an organic semiconductor layer over the passive layer; and providing a second electrode over the organic semiconductor layer.
Still yet another aspect of the present invention relates to a method of making an organic memory cell by providing a first electrode material in substrate wells and over the substrate; simultaneously removing a first portion of the first electrode material and converting a second portion of the first electrode material to a passive material to form first electrodes and passive layers in the wells; forming an organic semiconductor layer over the passive layer; and providing a second electrode over the organic semiconductor layer.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 4127412 (1978-11-01), Rule et al.
patent: 4663270 (1987-05-01), Potember et al.
patent: 5589692 (1996-12-01), Reed
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6208553 (2001-03-01), Gryko et al.
patent: 6212093 (2001-04-01), Lindsey
patent: 6272038 (2001-08-01), Clausen et al.
patent: 6314019 (2001-11-01), Kuekes et al.
patent: 63202
Chang Mark S.
Lopatin Sergey D.
Lyons Christopher F.
Ngo Minh Van
Oglesby Jane V.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Coleman W. David
LandOfFree
Methods of forming passive layers in organic memory cells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming passive layers in organic memory cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming passive layers in organic memory cells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3276040