Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-02-09
2000-12-12
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438255, 438398, H01L 2144, H01L 218242
Patent
active
061598496
ABSTRACT:
of A method of forming a dielectric layer includes the steps of forming an electrode on a microelectronic substrate, and forming depressions and protrusions on exposed portions of the electrode thereby increasing a surface area thereof. An exposed portion of the electrode including the depressions and protrusions is nitrified, and the electrode is not exposed to oxygen during and between the steps of forming the depressions and protrusions and nitrifying the exposed portion of the electrode. A nitride layer is then formed on a nitrified electrode. Related structures are also discussed.
REFERENCES:
patent: 5234862 (1993-08-01), Aketagawa et al.
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5372962 (1994-12-01), Hirota et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5394012 (1995-02-01), Kimura
patent: 5405801 (1995-04-01), Han et al.
patent: 5464791 (1995-11-01), Hirota
patent: 5486488 (1996-01-01), Kamiyama
patent: 5543347 (1996-08-01), Kawano et al.
patent: 5554557 (1996-09-01), Koh
patent: 5567637 (1996-10-01), Hirota
patent: 5590051 (1996-12-01), Yokozawa
patent: 5595937 (1997-01-01), Mikagi
patent: 5616511 (1997-04-01), Hirota
patent: 5623243 (1997-04-01), Watanabe et al.
patent: 5691228 (1997-11-01), Ping et al.
patent: 5754390 (1998-05-01), Sandhu et al.
patent: 5893980 (1999-04-01), Cho
patent: 5917213 (1999-06-01), Iyer et al.
patent: 5937314 (1999-08-01), Ping et al.
patent: 5960294 (1999-09-01), Zahurak et al.
H. Watanabe et al., An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes, Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, Aug. 27-19, 1991, pp. 478-480.
H. Watanabe et al., Hemispherical Grained Silicon (HSG-Si) Formation on In-Situ Phosphorous Doped Amorphous-Si Using The Seeding Method, Extended Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, Aug. 26-28, 1992, pp. 422-424.
H. Watanabe et al., A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs, 1992 IEEE, IEDM, 10.1.1-10.1.4, pp. 259-262.
Kang Seong-hun
Koh Young-lark
Lee Jung-kyu
Bowers Charles
Nguyen Thanh
Samsung Electronics Co,. Ltd.
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