Methods of forming NAND cell units

Details Methods of forming NAND cell units Methods of forming NAND cell units

2011-01-11

2011-01-11

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21495, C257S314000, C257S315000, C257S316000, C438S264000, C438S314000, C438S588000

Reexamination Certificate

active

07867844

ABSTRACT:
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

REFERENCES:
patent: 6239500 (2001-05-01), Sugimachi
patent: 6337245 (2002-01-01), Choi
patent: 7348236 (2008-03-01), Abbott et al.

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