Methods of forming metal silicide layers having insulator-filled

Details Methods of forming metal silicide layers having insulator-filled Methods of forming metal silicide layers having insulator-filled

1997-10-24

1999-12-14

Booth, Richard

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438595, 438704, 438906, 438974, H01L 213205, H01L 214763, H01L 21305

Patent

active

060017198

ABSTRACT:
Methods of forming metal silicide layers include the steps of forming electrically conductive lines that comprise the steps of forming a layer of polysilicon on a semiconductor substrate and then forming a layer of metal silicide on the polysilicon layer, opposite the substrate. The layer of metal silicide and the layer of polysilicon are then patterned as an electrically conductive line having sidewalls. The semiconductor substrate is then exposed to a cleaning agent that selectively etches the patterned layer of metal silicide at a faster rate than the patterned layer of polysilicon. The patterned layer of metal silicide is then thermally oxidized to define recess spacers extending adjacent sidewalls of the electrically conductive line. An electrically insulating layer is then formed on the electrically conductive line and on the recess spacers. The electrically insulating layer is then anisotropically etched to define insulating spacers on the recess spacers. These recess spacers reduce the likelihood that any subsequent reduction in size of the patterned metal silicide layer will cause the formation of voids in the insulating spacers and electrical shorts between the metal silicide layer and adjacent regions. In addition, according to one embodiment of the present invention, the thermally oxidizing step comprises thermally oxidizing the patterned layer of metal silicide at a faster rate than the patterned layer of polysilicon. Preferably, the oxidizing step comprises thermally oxidizing the patterned layer of metal silicide at a temperature of greater than about 800.degree. C.

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patent: 5811335 (1998-09-01), Santangelo et al.
Mayer, James W.; Electronic Materials Science: For Integrated Circuits in Si and GaAs; Oxidation of Silicides, pp. 294-295, 1990.

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