Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-14
2004-09-07
Karlsen, Ernest (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S674000, C438S686000
Reexamination Certificate
active
06787460
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to methods of forming integrated circuit devices and conductive contacts so formed in general, and more particularly, to methods of forming metal layers in integrated circuit devices and conductive contacts so formed.
BACKGROUND OF THE INVENTION
In general, electroplating can be carried out to form metal layers in integrated circuit (semiconductor) devices. In particular, since an integrated circuit device, such as an Ultra-High Speed Integrated circuit (ULSI), may operate much faster than other devices, copper (Cu) layers having relatively low resistance can be used to suppress the occurrence of ElectroMigration (EM) therein. It is known to use electroplating to form Cu wiring by patterning Cu layers. However, it may be difficult to pattern Cu using general etching methods because the copper may be prone to oxidization in air. Thus, the Cu wiring is generally formed using electroplating in combination with a damascene process.
However, the electroplating and damascene processes may promote voids in the Cu wiring. In detail, voids may occur when a contact hole, through which Cu deposited, or a trench used to form the wiring, is not completely filled or filled irregularly. The voids may result in the malfunction the electrical wiring of an integrated circuit device. Also, an electrolyte solution, which is used in the electroplating process, may remain in the void, thereby deteriorating the performance of a integrated circuit device.
FIG. 1
is a cross-sectional view of a void A occurring in a Cu layer
18
. Referring to
FIG. 1
, the Cu layer
18
is formed by electroplating and a damascene process to form Cu wiring in an integrated circuit device. An insulating layer
11
is formed on a integrated circuit substrate
10
. Then, the insulating layer
11
is patterned according to the damascene process to form a hole
12
and a trench
13
. An underlying layer, such as the integrated circuit substrate
10
or a lower conductive layer, can be electrically connected through the hole
12
. Thus, the hole
12
may be a contact hole or a via that passes through the insulating layer
11
. The trench
13
is formed as a line shape so as to pattern the Cu layer
18
as a wire on the insulating layer
11
.
Next, a barrier metal layer
14
, such as tantalum nitride (TaN), is formed on the resultant structure in which the trench
13
and the hole
12
are formed. Then, a Cu seed layer
16
is formed thereon. Thereafter, a Cu layer
18
is deposited using an electroplating process to fill the hole
12
.
During the deposition of the Cu layer
18
, it may be difficult to completely fill the hole
12
with the Cu layer
18
due to the high aspect ratio of the hole
12
, which may contribute to the formation of the void A during the electroplating process. A reduction in the design rule of integrated circuit device can result in an increase in the aspect ratio of a hole to three or more. In other words, the hole
12
can be three times or more times deeper than it is wide. Thus, it may be more likely that the void A can occur in the hole
12
because the edges of the mouth of the hole
12
are deposited faster than other flat portions, and thus the deposition at the mouth of the hole
12
can rapidly obstruct the opening of the hole
12
before the inner portion of the hole beneath the mouth of the hole
12
is completely filled with the Cu layer
18
, thereby reducing the reliability of the integrated circuit device. Moreover, an electrolyte solution used for the electroplating process may be trapped in the void A, thereby further reducing the reliability of the integrated circuit device.
SUMMARY OF THE INVENTION
Embodiments according to the invention can provide methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess. Pursuant to those embodiments, a recess can be formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask can be formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall that is free of the selective electroplating mask. The exposed portion of the side wall can be electroplated with a metal.
In embodiments of conductive contacts according to the invention, a conductive contact can include a recess in an integrated circuit substrate. The recess includes a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of a surface of the insulating layer and the side wall. A selective electroplating mask is on the side wall to provide a covered portion of the side wall adjacent to the edge and is not on a portion of the side wall adjacent to the bottom. An electroplated metal is on the portion of the side wall adjacent to the side wall.
In further method embodiments according to the invention, a recess is etched in a surface of an insulating layer wherein the recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A trench is etched in the surface of the insulating layer on the recess. The trench is wider than the recess and exposes the edge of the recess. A barrier metal layer is formed in the recess and in the trench and on the insulating layer and a seed layer is formed on the barrier metal layer. A selective electroplating mask is formed on the seed layer on the side wall adjacent to the edge to provide a covered portion of the side wall and not on the side wall beyond adjacent to the edge to provide a portion of the side wall that is not covered by the selective electroplating mask. A first metal is formed in the recess to beneath a level of the electroplating mask on the exposed portion of the side wall and not on the covered portion of the side wall. A second metal is formed in the recess and in the trench on the first metal and on the selective electroplating mask and the second metal layer is planarized to expose the selective electroplating mask.
In further method embodiments according to the invention, a first recess is etched in a surface of a first insulating layer wherein the first recess has a first side wall inside the first recess, a first bottom inside the first recess, and a first edge at a boundary of the surface of the first insulating layer and the first side wall. A first barrier metal layer is formed in the first recess and on the surface of the first insulating layer and a first seed layer is formed on the first barrier metal layer. A first selective electroplating mask is formed on the first seed layer on the first side wall adjacent to the first edge to provide a covered portion of the first side wall and not on the first side wall beyond adjacent to the first edge to provide an exposed portion of the first side wall that is free of the selective electroplating mask. A first metal is formed on the exposed portion of the first side wall in the first recess and protrudes beyond the first recess and is not formed on a portion of the first selective electroplating mask on the surface of the first insulating layer spaced apart from the first edge. The first metal is planarized to expose the first selective electroplating mask on the first edge. A second insulating layer is formed on the first metal and a surface of the second insulating layer is etched to form a second recess that exposes the first metal, wherein the second recess has a second side wall inside the second recess, a second bottom inside the second recess, and a second edge at a boundary of the surface of the second insulating layer and the second side wall. A second barrier metal layer is formed in the second recess and on the surface of the second insulating layer and a second seed layer is formed on the second barrier metal layer. A second selective electroplating mask is formed in the second recess on the second side wall adjacent to the second edge to provi
Choi Gil-heyun
Choi Seung-man
Kang Sang-bum
Lee Hyo-jong
Karlsen Ernest
Kilday Lisa
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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