Methods of forming memory circuitry

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S211000, C438S257000, C257S314000, C257S315000, C257S316000, C257S320000, C257S326000, C257SE21640, C257SE21660, C257SE29170

Reexamination Certificate

active

07419865

ABSTRACT:
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

REFERENCES:
patent: 5250457 (1993-10-01), Dennison
patent: 5387533 (1995-02-01), Kim
patent: 5563089 (1996-10-01), Jost et al.
patent: 5686747 (1997-11-01), Jost et al.
patent: 5728617 (1998-03-01), Tseng
patent: 5821140 (1998-10-01), Jost et al.
patent: 5834349 (1998-11-01), Tseng
patent: 5918122 (1999-06-01), Parekh et al.
patent: 5981333 (1999-11-01), Parekh et al.
patent: 6010935 (2000-01-01), Doan
patent: 6015983 (2000-01-01), Parekh
patent: 6037218 (2000-03-01), Dennison
patent: 6060351 (2000-05-01), Parekh et al.
patent: 6107189 (2000-08-01), Wald et al.
patent: 6140172 (2000-10-01), Parekh
patent: 6177695 (2001-01-01), Jeng
patent: 6180450 (2001-01-01), Dennison et al.
patent: 6214727 (2001-04-01), Parekh
patent: 6228710 (2001-05-01), Parekh et al.
patent: 6228738 (2001-05-01), Parekh et al.
patent: 6232176 (2001-05-01), Parekh et al.
patent: 6238971 (2001-05-01), Parekh et al.
patent: 6245631 (2001-06-01), Agarwal et al.
patent: 6284641 (2001-09-01), Parekh
patent: 6297525 (2001-10-01), Parekh et al.
patent: 6300215 (2001-10-01), Shin
patent: 6312988 (2001-11-01), Lowrey et al.
patent: 6323080 (2001-11-01), Parekh
patent: 6329682 (2001-12-01), Parekh et al.
patent: 6329684 (2001-12-01), Parekh et al.
patent: 6334692 (2002-01-01), Hsueh
patent: 6337274 (2002-01-01), Hu et al.
patent: 6359302 (2002-03-01), Parekh et al.
patent: 6368962 (2002-04-01), Hu et al.
patent: 6376301 (2002-04-01), Parekh et al.
patent: 6376380 (2002-04-01), Tang et al.
patent: 6383868 (2002-05-01), Parekh et al.
patent: 6407455 (2002-06-01), Wald et al.
patent: 6429476 (2002-08-01), Suzuki
patent: 6458649 (2002-10-01), Zahurak et al.
patent: 6468859 (2002-10-01), Parekh et al.
patent: 6486060 (2002-11-01), Hermes et al.
patent: 6500709 (2002-12-01), Parekh et al.
patent: 6524907 (2003-02-01), Parekh et al.
patent: 6589876 (2003-07-01), Tran
patent: 6617635 (2003-09-01), Parekh et al.
patent: 2004/0110341 (2004-06-01), Park et al.

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