Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-05-10
2005-05-10
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S710000, C438S691000, C438S693000, C438S694000
Reexamination Certificate
active
06890858
ABSTRACT:
In one aspect, the invention encompasses a semiconductor processing method of forming a material over an uneven surface topology. A substrate having an uneven surface topology is provided. The uneven surface topology comprises a valley between a pair of outwardly projecting features. A layer of material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the outwardly projecting features of the surface topology and has a gap over the valley. The layer is etched, and the etching forms protective material within the gap while removing an outermost surface of the layer. The etching substantially does not remove the material from the bottom of the gap. In another aspect, the invention encompasses a semiconductor processing method of forming a material over metal-comprising lines. A first insulative material substrate is provided. A pair of spaced metal-comprising lines are formed over the substrate. The spaced metal-comprising lines define an uneven surface topology which comprises the lines and a valley between the lines. A layer of second insulative material is formed over the uneven surface topology. The layer comprises outwardly projecting portions over the lines and having a gap over the valley. The layer of second insulative material is subjected to an etch which forms a protective material at the bottom of the gap. The protective material substantially prevents the second insulative material from being etched from the bottom of the gap.
REFERENCES:
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4630357 (1986-12-01), Rogers et al.
patent: 5366590 (1994-11-01), Kadomura
patent: 5458919 (1995-10-01), Okano et al.
patent: 5468342 (1995-11-01), Nulty et al.
patent: 5549786 (1996-08-01), Jones et al.
patent: 5679606 (1997-10-01), Wang et al.
patent: 5759906 (1998-06-01), Lou
patent: 5783100 (1998-07-01), Blalock et al.
patent: 5798016 (1998-08-01), Oehrlein et al.
patent: 5814564 (1998-09-01), Yao et al.
patent: 5871658 (1999-02-01), Tao et al.
patent: 5872061 (1999-02-01), Lee et al.
patent: 5880037 (1999-03-01), Arleo
patent: 5962344 (1999-10-01), Tu et al.
patent: 5965463 (1999-10-01), Cui et al.
patent: 5972235 (1999-10-01), Brigham et al.
patent: 6008103 (1999-12-01), Hoepfner
patent: 6025255 (2000-02-01), Chen et al.
patent: 6043152 (2000-03-01), Chang et al.
patent: 6106678 (2000-08-01), Shufflebotham et al.
patent: 6211065 (2001-04-01), Xi et al.
patent: 6271141 (2001-08-01), Juengling et al.
patent: 6376911 (2002-04-01), Ryan et al.
patent: 6479388 (2002-11-01), Juengling et al.
S. Wolf et al.: “Etching Silicon and Silicon Dioxide In Fluorocarbon-Containing Plasmas”; vol. 1, Silicon Processing for the VLSI Era, 1986; pp. 547-554.
Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, USA, pp. 51-57, 176-246, 1990.
Donohoe Kevin G.
Juengling Werner
Anderson Matthew
Micro)n Technology, Inc.
Norton Nadine G.
Wells St. John P.S.
LandOfFree
Methods of forming materials over uneven surface topologies,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming materials over uneven surface topologies,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming materials over uneven surface topologies,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3446871