Methods of forming isolation trenches in integrated circuits...

Details Methods of forming isolation trenches in integrated circuits... Methods of forming isolation trenches in integrated circuits...

1999-03-22

2001-04-17

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S591000, C438S592000, C117S094000

Reexamination Certificate

active

06218273

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit fabrication in general and more particularly to shallow trench isolation in integrated circuits
BACKGROUND OF THE INVENTION
In integrated circuits, such as integrated circuit memories, an isolation region may be provided between active regions of the integrated circuit. Consequently, the size of the isolation region may affect the level of integration of the integrated circuit. It is known to use processes such as Selective Polysilicon Oxidation (SEPOX), Recessed Polysilicon Spacer (RPSL), or Local Oxidation of Silicon (LOCOS). These processes may, however, exhibit problems that affect the reliability of the integrated circuit. For example, the LOCOS process may exhibit “bird's beak” at boundaries between a pad oxide film and a nitride film, thereby possibly affecting the reliability of the integrated circuit.
It is also known to form shallow isolation trenches to a depth of about 2500 Angstroms (Å). If the depth of trench is less than 2500 Å, the degree of isolation may not be sufficient. However, the need to achieve high levels of integration in the integrated circuit may limit the width of the trench which may limit the aspect ratio of the isolation trench (trench depth/trench width). In other words, as the width of the trench diminishes, the aspect ratio of the isolation trench may also increase. Accordingly, it may be difficult to fill the trench with the isolation material. In particular, a high aspect ratio of the trench may promote the formation of seams in the isolation trench which may reduce the reliability of the integrated circuit.
It is known to provide trench isolation in an integrated circuit substrate
11
using high density low pressure plasma Chemical Vapor Deposition (CVD) to reduce the seams, as shown in
FIGS. 1A through 1F
. According to
FIG. 1A
, a pad oxide film
13
of thickness 100 Å and a nitride film
15
of thickness 2000 Å are formed on an integrated circuit substrate
11
subsequently. A high temperature oxide film
17
is formed on the nitride film
15
.
The high temperature oxide film
17
is patterned using photoresist as a mask and etched until portions of the surface of nitride film
15
are exposed whereafter the photoresist is removed. The remaining portion of the high temperature oxide film
17
is used as an etch mask to remove exposed portions of the nitride film
15
, and the pad oxide film
13
. The resulting structure is used to etch the integrated circuit substrate
11
to form a trench
19
in the integrated circuit substrate
11
of a depth of about 2500 Å.
As shown in
FIG. 1B
, a first oxide film
21
is thermally grown on the bottom and sides of the isolation trench
19
to a thickness in a range between 100 and 500 Å. The first oxide film
21
may repair some of the damage done to the bottom and sides of the isolation trench
19
during etching. Then, the first oxide film
21
is plasma-treated and a first Undoped Silicate Glass (USG) film
23
is formed to a thickness of about 1500 Å using a tetra-ethyl ortho silicate (TEOS) CVD process as shown in FIG.
1
C. The first oxide film
21
is plasma treated to promote a uniform thickness for the first USG film
23
formed on the first oxide film
21
in the isolation trench
19
by preventing a portion of the first USG film
23
near the top of the isolation trench
19
from having a greater thickness than other portions of that relying upon the surface state of the underlying first oxide film
21
.
As shown in
FIG. 1D
, the first USG film
23
is etched back using an argon sputtering process thereby leaving the first USG film
23
on the first oxide film
21
in the isolation trench
19
and the portion of the first USG film
23
near the top of the isolation trench
19
having a predetermined slope. Removing the portion of the first USG film
23
near the top of the isolation trench
19
may promote the filling of an insulating film from the trench
19
during subsequent steps of the process.
As shown in
FIG. 1E
, a second USG film
25
is formed on the high temperature oxide film
17
and in the isolation trench
19
to a thickness in range of 5000 to 7000 Å and a second oxide film
27
is formed on the second USG film
25
by Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS) CVD. The first and second USG films
23
,
25
are densified by heating to a temperature of about 1000° C. for an hour in a nitrogen environment.
As shown in
FIG. 1F
, the isolation trench
19
is planarized to expose the pad oxide film
13
using CMP. The pad oxide film
13
is wet etched to expose the active areas of the integrated circuit substrate
11
.
Unfortunately, as the aspect ratio of the isolation trench
19
increases it may be increasingly difficult to fill the second USG film
25
in the isolation trench
19
, so that adequate isolation can not be provided between the active areas of the integrated circuit substrate
11
without plasma-treating the first oxide film
21
(which may complicate the process of forming the trench isolation structure).
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide for an improvement in the fabrication of integrated circuits.
It is another object of the present invention to allow further reduction in the complexity of the fabrication of integrated circuits.
It is a further object of the present invention to allow improvement in the reliability of integrated circuits so formed.
These and other objects are provided by forming a first isolation trench in the integrated circuit substrate between active regions in the integrated circuit substrate. An insulating layer is formed in the first isolation trench, wherein the insulating layer includes a portion that protrudes from the first isolation trench. A second isolation trench is formed on the first isolation trench self-aligned to the active regions in the integrated circuit substrate, wherein the second isolation trench includes the protruding portion of the insulating layer.
The protruding portion of the insulating material that remains adds to the depth of the isolation trench, thereby allowing the depth of the first isolation trench to be less than in conventional integrated circuit fabrication which may avoid the development of a seam in the insulating layer without a plasma treatment step. Consequently, the present invention may provide a simpler method of fabricating isolation trenches in integrated circuits. In contrast, in some conventional methods the protruding portion of the insulating layer is removed which may require the isolation trench to be formed to an initial depth which provides adequate insulation.
In one embodiment, an epitaxial layer is grown on the integrated circuit substrate around the protruding portion of the insulating layer to a thickness about equal to the depth of the protruding portion of the insulating layer.


REFERENCES:
patent: 4250568 (1981-02-01), Grassl
patent: 4929302 (1990-05-01), Valette
patent: 5293063 (1994-03-01), Anceau
patent: 5448180 (1995-09-01), Kienzler et al.
patent: 5859459 (1999-01-01), Ikeda
patent: 5989997 (1999-11-01), Lin et al.
patent: 6037261 (2000-03-01), Jost et al.
patent: 6040609 (2000-03-01), Frisina et al.

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