Methods of forming integrated circuits using masks to...

Details Methods of forming integrated circuits using masks to... Methods of forming integrated circuits using masks to...

2001-06-26

2004-07-27

Lee, Eddie (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S252000, C438S395000, C438S246000, C257S296000, C257S345000

Reexamination Certificate

active

06767787

ABSTRACT:

CLAIM FOR FOREIGN PRIORITY
This application claims priority to Korean Application No. 2000-35707, filed Jun. 27, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to methods of forming integrated circuits and to integrated circuits in general, and more particularly, to methods of forming integrated circuit memory devices using ion implantation and to integrated circuits formed using same.
BACKGROUND
In dynamic random access memories (DRAMs), data can be recorded by storing charge in a capacitor of a memory cell. To keep data recorded in DRAMs, the data may need to be refreshed periodically. Data retention time is one of the characteristics used to determine the performance of DRAMs. One of the factors that influences data retention time is junction leakage current. Junction leakage current can be produced by an electric field at a pn junction boundary or by substrate defects in a depletion region. Decreasing the junction leakage current may increase data retention time and thereby improve the performance of DRAMs.
As the integration density of DRAMs increases, the size of a transistor included therein may decrease. Decreasing the size of a transistor may decrease the length of a channel region, thereby causing short channel effects such as a decrease in the threshold voltage V
T
of the transistor. A doping concentration can be increased gradually during channel ion-implantation to compensate for a decrease in V
T
and thereby adjust V
T
to a proper level.
FIG. 1
is a cross-sectional view of a conventional channel ion-implantation used to adjust V
T
. A p-type dopant can be ion-implanted into an entire p-type integrated circuit substrate
10
, including a isolation region
12
, to form a doping region
20
without using an ion-implantation mask. Thereafter, a gate electrode
24
and an n-type source/drain region
26
can be formed.
When the channel ion-implantation is performed throughout the entire substrate
10
, as shown in
FIG. 1
, the source/drain region
26
can be influenced by the doping region
20
formed by the channel ion-implantation. In this case, when the doping concentration is increased during the channel ion-implantation to prevent a short channel effect, substrate defects may occur between the isolation region
12
and the source/drain region
26
or in a depletion region.
Since the dopant implanted during the channel ion-implantation may have a polarity that is opposite a dopant that is ion-implanted into the source/drain region, an electric field at the pn junction boundary may be increased, thereby increasing junction leakage current. Consequently, data retention time may be decreased. Moreover, channel ion-implantation performed at a high concentration may increase junction capacitance. As a result, when charge stored in the capacitors of memory cells is read, the information may be affected by noise, so that a sensing margin is decreased.
FIGS. 2A and 2B
are cross-sectional views that illustrate conventional channel ion-implantation to adjust V
T
. A doping region
50
can be formed by implanting a p-type dopant
46
into only a region where a gate electrode
54
will be formed on an integrated circuit substrate
40
, using a reverse gate pattern
44
, formed of a photoresist film, as an ion-implantation mask. Thereafter, the gate electrode
54
can be formed on the doping region
50
.
According to some conventional methods described with reference to
FIGS. 2A and 2B
, as the integration density of devices increases, it may become difficult to form the reverse gate pattern
44
used as a channel ion-implantation mask. In addition, when conventional methods are applied to the manufacturing of devices having a small pitch between gate electrodes
54
, various problems can be caused by the misalignment of the mask or by variation in the critical dimension in a channel ion-implantation step or a gate electrode-patterning step followed by the channel ion-implantation step. For example, when the reverse gate pattern
44
is misaligned, the doping region
50
formed at the edge of an isolation region
42
may be affected by the junction leakage current. Accordingly, the operation of a device may be adversely affected.
In other conventional methods, channel ion-implantation can be performed using a reverse gate pattern as shown in
FIG. 2A
, and then a gate electrode may be formed to be self-aligned to the reverse gate pattern. However, in this method it may be difficult to form the structure of a gate electrode having multiple layers. In addition, processes of forming self-aligned contacts, such as a landing pad self-aligned with respect to a gate electrode may be impracticable.
SUMMARY OF THE INVENTION
Embodiments of methods according to the present invention may allow a channel region to be formed between isolation regions of an integrated circuit substrate. Pursuant to these embodiments, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shielded portion of the substrate adjacent to the isolation region and an exposed portion of the substrate spaced apart from the isolation region having the shielded portion therebetween. A channel region can be formed in the exposed portion of the substrate.
In some embodiments according to the present invention, a first level of ions can be implanted in the shielded region adjacent to the isolation region. A second level of ions can be implanted in the channel region spaced apart from the isolation region, wherein the second level is greater than the first level.
In some embodiments according to the present invention, boron ions are implanted in the exposed region and then boron difluoride ions are implanted in the exposed region. In some embodiments according to the present invention, a gate electrode can be formed on the channel region and a contact can be formed on the shielded region. Source and drain regions can be formed in the channel region self aligned to the gate electrode.


REFERENCES:
patent: 5395784 (1995-03-01), Lu et al.
patent: 6008085 (1999-12-01), Sung et al.
patent: 6165825 (2000-12-01), Odake
patent: 6329233 (2001-12-01), Pan et al.
patent: 6359301 (2002-03-01), Kuroda
patent: 60263430 (1985-12-01), None
patent: 10056147 (1998-02-01), None
Official Action, Korean Application No. 10-2000-0035707, Jan. 28, 2002 (2 pages).
Daewon Ha et al.; EntitledSelf-Aligned Local Channel Implantation Using Reverse Gate Pattern for Deep Submicron Dynamic Random Access Memory Cell Transistors, Japanese J. Applied Physics, vol. 37 (1998) pp 1059-1063.

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