Methods of forming integrated circuitry, methods of forming...

Details Methods of forming integrated circuitry, methods of forming... Methods of forming integrated circuitry, methods of forming...

1998-12-01

2001-04-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S303000, C438S305000, C438S947000

Reexamination Certificate

active

06211026

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming integrated circuitry, to methods of forming elevated source/drain regions of a field effect transistor, and to methods of forming field effect transistors.
BACKGROUND OF THE INVENTION
As integrated circuitry device dimensions continue to shrink, problems such as short channel effects, source-drain punchthrough, and hot electron susceptibility become ever present, particularly in the deep sub-half-micron regime. These effects have, in the past, been addressed by additional masking levels and through the incorporation of lightly doped drain (LDD) engineering.
This invention arose out of concerns associated with providing improved integrated circuitry devices while reducing problems associated with short channel effects, source-drain punchthrough, and hot electron susceptibility, particularly in the deep sub-half-micron regime.
SUMMARY OF THE INVENTION
Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned, with conductivity-modifying impurity being subsequently provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.


REFERENCES:
patent: 4587710 (1986-05-01), Tsao
patent: 4784971 (1988-11-01), Chiu et al.
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5314832 (1994-05-01), Deleonibus
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5395787 (1995-03-01), Lee et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5504031 (1996-04-01), Hsu et al.
patent: 5571733 (1996-11-01), Wu et al.
patent: 5637518 (1997-06-01), Prall et al.
patent: 5674774 (1997-10-01), Pasch et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5773358 (1998-06-01), Wu et al.
patent: 5780349 (1998-07-01), Naem
patent: 5811329 (1998-09-01), Ahmad et al.
patent: 5827768 (1998-10-01), Lin et al.
patent: 5851883 (1998-12-01), Gardner et al.
patent: 5885877 (1999-03-01), Gardner et al.
patent: 5897357 (1999-04-01), Wu et al.
patent: 5902125 (1999-05-01), Wu
patent: 5915183 (1998-06-01), Gambino et al.
patent: 5953605 (1999-09-01), Kodama
patent: 6001698 (1999-12-01), Kodura
Wolf, “Silicon processing for the VLSI era,” vol. 1, ppg 320-323 and 520-523, 1986.*
Nakahara et al, “Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS,” IEEE 1996 Symp. on VLSI Tech Dig. of Tech. Papers, pp. 174, 1996.*
Rodder, et al “Raised source/drain MOSFET with Dual Sidwall Spacers,” IEEE Elect. Dev. Lett. vol. 12, No. 3, , ppg 89, 1991.

Affiliated with

Also associated with

Rating

Methods of forming integrated circuitry, methods of forming... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming integrated circuitry, methods of forming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming integrated circuitry, methods of forming... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2488847