Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-13
2002-03-12
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S640000, C438S700000
Reexamination Certificate
active
06355554
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to microelectronic device fabrication methods, in particular, to methods for fabricating interconnections including a contact hole and an interconnection line in microelectronic devices.
BACKGROUND OF THE INVENTION
When forming an interconnection to a microelectronic layer of a microelectronic device, a contact hole typically is formed in an insulating layer covering the microelectronic layer, and the contact hole is filled with a conductive material to form an interconnection. Several techniques have been developed for filling contact holes, including widely-used selective tungsten, blanket tungsten, laser reflow, high temperature deposition, and aluminum reflow processes. As the density of the integration of microelectronic devices has increased, however, the cross-sectional area of contact holes used for interconnections has generally decreased, leading to a need to use contact holes having increased aspect ratio. It may be difficult to fill such high aspect ratio contact holes using conventional techniques.
Long throw sputtering (LTS) and high-pressure reflow processes have been developed for filling high aspect ratio contact holes. In the LTS process, improved step coverage, and thus improved contact hole filling capability, may be achieved by increasing the distance between a target and a wafer to be processed for improving an initial step coverage of the contact hole. However, a void may be formed due to reduced deposition speed of the sputtered conductive material and asymmetry between the edge and the center of the contact hole where the conductive material is deposited. Such problems may make it difficult to fill a contact hole having an aspect ratio of 4 or greater.
High-pressure reflow processes typically involve deposition of aluminum on a contact hole, and subsequent treatment under high temperature and pressure, for example, 400° C. and 600 MPa, to reflow the deposited material into the contact hole. However, although the conventional high temperature reflow processes may be effective for filling contact holes having an aspect ratio of 10 or greater, they may not be effective for filling large diameter contact holes.
FIGS. 1A and 1B
are cross-sectional views illustrating conventional techniques of forming an interconnection according to the prior art. Referring to
FIGS. 1A and 1B
, a contact hole is formed in an insulating layer
12
on a microelectronic substrate
10
using, for example, a photolithography process. The contact hole is then cleaned using a hydrogen fluoride, and a barrier layer
14
and an aluminum layer
16
are deposited on the resultant structure. The deposited aluminum is then reflowed by applying high temperature and pressure, for example, 400° C. and 600 MP, which causes the deposited aluminum to fill the contact hole as illustrated in FIG.
1
B.
As described above, although the conventional high temperature reflow processes may be effective for filling contact holes having an aspect ratio of 10 or greater, it may not be effective for filling large diameter contact holes. That is, if there is a failure to bridge a large contact hole, this may lead to the generation of a void A in the contact hole during the reflow process as shown in FIG.
1
B. In addition, if there are a plurality of contact holes having different contact sizes in the same layer, it is more difficult to fill the contact holes without the generation of voids.
FIGS. 5A
to
5
C are cross-sectional views illustrating a conventional aluminum reflow technique for forming an interconnection when a plurality of contact holes having different contact sizes are formed in the same insulation layer. Referring to
FIG. 5A
, an insulation layer
62
is formed on a substrate
60
having a planarized surface. A plurality of contact holes
64
a
and
64
b
are formed in the insulation layer
62
by a general photolithography technique. The contact hole
64
a
has a contact diameter of “a” and the other contact hole
64
b
has a contact diameter of “b” which is larger than a contact size of “a”. Then, an aluminum layer
66
is deposited on the exposed surface of the substrate
60
and the insulation layer
62
with a thickness of “T1”.
Referring to
FIG. 5B
, a conventional aluminum reflow process is performed on the resultant structure of
FIG. 5A
by supplying heat. At this time, the aluminum layer
66
is flowed into the plurality of contact holes
64
a
and
64
b
, but the relatively small contact hole
64
a
may include a void
67
and the relatively large contact hole
64
b
may be not fully filled with the aluminum.
Referring to
FIG. 5C
, a Chemical-Mechanical Polishing(CMP) process is performed on the resultant structure for planarization, to expose the insulation layer
62
. At this time, although the surface of the small contact hole
64
a
is planarized, the large contact hole
64
b
is not sufficiently planarized.
In the meantime, in the above aluminum reflow process, if the thickness T1 of the deposited aluminum is controlled on the basis of the large contact hole
64
b
, the thickness of the aluminum layer to be deposited is increased, to thereby bridge the aluminum layer
66
at the upper portion of the small contact hole
64
a
. Therefore, in a subsequent reflow process, a void is formed in the small contact hole
64
a
. This void also acts as a factor of deterioration of device.
For multi-layered microelectronic devices, the aspect ratio of contact holes may be even further increased, causing problems such as a non-planarization of interconnection layers, inferior step coverage, metal shorts, low yields, and reduced reliability. In order to address many of these problems, damascene techniques have been developed.
FIG. 2
is a cross-sectional view of a conventional dual damascene structure. The dual damascene structure includes a stud (contact hole) connected to the underlying substrate
10
and an interconnection line with a predetermined depth in the insulation layer
12
. If the stud is located apart from a center of the interconnection line, the dual damascene structure has substantially asymmetrical characteristics for filling with a material. In the meanwhile, if the stud is located in a center of the interconnection lines, the dual damascene structure has also asymmetrical characteristics for filling due to the differences of width and depth between the stud and the interconnection lines. These damascene techniques typically involve etching a planar insulating layer to form a via, filling the via with metal
18
, and removing excessive metal overlying the insulating layer using chemical mechanical polishing (CMP). Sputtered aluminum or tungsten deposited by chemical vapor deposition (CVD) are commonly used as the filling metal.
For CVD-deposited tungsten, a titanium nitride layer may be used as an adhesion layer, and the adhesion layer lifted by tungsten fluoride (WF
6
) gas. However, during planarization using CMP, a defect may be formed in the metal fill due to a seam which is typically formed during chemical vapor deposition of tungsten. For sputtered aluminum, the contact hole may not be fully filled due to an inferiority of step coverage, typical of the sputtering process. This may resulting in the formation of a void B, as illustrated in FIG.
2
.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide improved methods for forming interconnections including a contact hole and an interconnection line in microelectronic devices which reduce the probability of voids and other defects.
It is another object of the present invention to provide methods for forming an interconnections in microelectronic devices which are suitable for use with large contact holes.
It is still another object of the present invention to provide methods for forming a contact holes in microelectronic devices which are suitable for use with a plurality of contact holes having a different contact size.
It is yet still another object of the present invention to provide methods for forming
Choi Gil-heyun
Kim Byeong-jun
Lee Eung-joon
Collins D. M.
Myers Bigel & Sibley & Sajovec
Picardat Kevin M.
Samsung Electronics Co,. Ltd.
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