Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-31
2002-01-01
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S285000, C438S303000
Reexamination Certificate
active
06335234
ABSTRACT:
TECHNICAL FIELD
This application relates to methods of forming field effect transistors and related field effect transistor constructions.
BACKGROUND OF THE INVENTION
Transistors find use in a wide range of integrated circuits. One type of transistor is the metal-oxide-semiconductor field effect transistor or MOSFET. Typical MOSFETs include source/drain diffusion regions which are disposed within a substrate and a conductive gate which overlies a channel region intermediate the source/drain diffusion regions. as In some MOSFETs, placement of a desired voltage on the conductive gate enables a channel to be formed between the source/drain diffusion regions. With the channel being formed, current can be made to flow between the source and the drain. There are a number of different types of MOSFETs such as NMOS and PMOS field effect transistors.
NMOS field effect transistors are typically formed on a p-type substrate or p-well. The channel in an NMOS transistor is usually formed through provision of a positive gate voltage on the transistor which attracts minority electrons within the p-type substrate into the channel region. PMOS field effect transistors are typically formed on an n-type substrate or n-well. The channel in PMOS transistors is typically formed through provision of a negative gate voltage on the transistor gate which attracts minority holes from the n-type substrate into the channel region to form the channel. CMOS (Complementary Metal Oxide Semiconductor) devices utilize both NMOS and PMOS transistors.
An important parameter in MOS transistor is the threshold voltage V
t
, which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an n-channel device (NMOS) must be larger than some value V
t
before a conducting channel is induced. Similarly, a p-channel device (PMOS) requires a gate voltage which is more negative than some threshold value to induce the required positive charge in the channel. A valuable tool for controlling threshold voltage is ion implantation. Because very precise quantities of impurity can be introduced into the substrate by this method, it is possible to maintain close control of V
t
. For example, introduction of a p-type impurity into a p-channel PMOS device can make V
t
less negative. This is because the channel region is made more p-type and therefore a lower magnitude of negative voltage is required to induce holes within the channel region.
As MOS transistors are made smaller and smaller, they become susceptible to so-called short channel effects. Short channel effects can be divided into (a) those that impact V
t
, (b) those that impact subthreshold currents, and (c) those that impact I-V behavior beyond threshold. Short channel effects include punch through which normally occurs as a result of the widening of the drain depletion region when the reverse-bias voltage on the drain is increased. The electric field of the drain may eventually penetrate into the source region and thereby reduce the potential energy barrier of the source-to-body junction. When this occurs, more majority carriers in the source region have enough energy to overcome the barrier, and an increased current then flows from the source to the body, some of which is collected by the drain. One way of reducing the electric field of the drain and hence the risk of punch through is to form so-called halo regions proximate the source/drain regions of a transistor. Halo regions are described in more detail in the texts which are incorporated by reference below.
One type of MOS transistor is a buried channel PMOS. Buried channel PMOS transistors typically have a p−diffusion region disposed within the substrate underneath the gate and between the source/drain diffusion regions. The elevational thickness of the p−diffusion region within the substrate is referred to as gamma-j. One goal in the design of buried channel PMOS transistors is to reduce gamma-j to improve control over current leakage. It is also desirable to provide the p−region as close to the gate as possible to provide for more gate control.
For a more detailed treatment of short channel effects and other relevant semiconductor processing concerns, the reader is referred to two texts:
Wolf, Silicon Processing for the VLSI Era,
Volume 2, Chapters 5 and 6; and Streetman,
Solid State Electronic Devices,
Fourth Edition, both of which are expressly incorporated by reference herein.
This invention arose out of concerns associated with improving the methodology through which MOS devices are fabricated, and improving the resultant MOS structures.
SUMMARY OF THE INVENTION
Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are provided into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.
REFERENCES:
patent: 4612258 (1986-09-01), Tsang
patent: 4649629 (1987-03-01), Miller et al.
patent: 4771014 (1988-09-01), Liou et al.
patent: 5171700 (1992-12-01), Zamanian
patent: 5235204 (1993-08-01), Tsai
patent: 5434093 (1995-07-01), Chau et al.
patent: 5463237 (1995-10-01), Funaki
patent: 5534447 (1996-07-01), Hong
patent: 5538913 (1996-07-01), Hong
patent: 5548143 (1996-08-01), Lee
patent: 5576574 (1996-11-01), Hong
patent: 5595919 (1997-01-01), Pan
patent: 5605855 (1997-02-01), Chang et al.
patent: 5643815 (1997-07-01), Vu et al.
patent: 5658811 (1997-08-01), Kimura et al.
patent: 5670397 (1997-09-01), Chang et al.
patent: 5688700 (1997-11-01), Kao et al.
patent: 5698461 (1997-12-01), Liu
patent: 5712501 (1998-01-01), Davies et al.
patent: 5736446 (1998-04-01), Wu
patent: 5747356 (1998-05-01), Lee et al.
patent: 5766998 (1998-06-01), Tseng
patent: 5773348 (1998-06-01), Wu
patent: 5773863 (1998-06-01), Burr et al.
patent: 5849615 (1998-12-01), Ahmad et al.
patent: 5854135 (1998-12-01), Ko
patent: 5893740 (1999-04-01), Chang et al.
patent: 5899719 (1999-05-01), Hong
patent: 5899732 (1999-05-01), Gardner et al.
patent: 5917219 (1999-06-01), Nandakumar et al.
patent: 5930615 (1999-07-01), Manning
patent: 6025232 (2000-02-01), Wu et al.
patent: 6025235 (2000-02-01), Krivokapic
patent: 6025635 (2000-02-01), Krivokapic
patent: 6063677 (2000-05-01), Rodder et al.
patent: 6078086 (2000-06-01), Park
patent: 6114211 (2000-09-01), Fulford et al
patent: 6121089 (2000-09-01), Zeng et al.
patent: 6127700 (2000-10-01), Bulucea
patent: 6146953 (2000-11-01), Lee et al.
patent: 6147383 (2000-11-01), Kuroda
patent: 6163053 (2000-12-01), Kawashima
patent: 6169315 (2001-01-01), Son
patent: 6177336 (2001-01-01), Lin et al.
patent: 9-135022 (1997-05-01), None
Wolf et al., Silicon Processing for the VLSI Era: vol. 1—Processing Technology, Lattice Press 1986, p. 323, No Month.
Hatab Paul
Wu Zhiqiang
Lebentritt Michael S.
Micro)n Technology, Inc.
Wells St. John et al.
LandOfFree
Methods of forming field effect transistors and related... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming field effect transistors and related..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming field effect transistors and related... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2816664