Methods of forming electrically conductive lines in...

Details Methods of forming electrically conductive lines in... Methods of forming electrically conductive lines in...

1999-04-01

2001-01-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S589000, C438S592000, C438S597000, C257S296000

Reexamination Certificate

active

06171942

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits in general, and more particularly, to the formation of contacts in integrated circuits.
BACKGROUND OF THE INVENTION
As the level of integration of integrated circuits increases there may be a decrease in the size of conductive lines, such as contacts, formed in the integrated circuits. Decreasing the size of the contacts, however, may increase the contact resistance.
It is known to use a Self-Aligned Silicide (Salicide) process in integrated circuits having 0.35 um line width to decrease the resistance of contacts. Using a Salicide process may be problematic in some higher density integrated circuits, such as Dynamic Random Access Memories (DRAMs). For example, the Salicide process may adversely affect the capacitance of storage cells in a memory array of a DRAM.
In addition, forming low resistance contacts using a Silicide film may add steps to the photolithography process in which a Silicide Blocking Layer (SBL) is formed on portions of the integrated circuit. Also, additional margin may need to be added to the masks used in the photolithography steps to compensate for misalignment.
FIGS.
1
-
7
illustrate conventional methods of forming integrated circuit structures having Silicide contacts in two regions of the integrated circuit: a memory array A and a peripheral region B which includes areas outside the memory array A. Gate electrodes in the memory array region A may be formed with a closer spacing than the gate electrodes formed in the peripheral region B. According to
FIG. 1
, an integrated circuit substrate
10
is formed which includes Shallow Trench Isolation regions (STI)
12
. The STI regions
12
may be formed using a field oxide layer. A plurality of gate electrodes
14
are formed on the integrated circuit substrate
10
with spacers
16
formed on sidewalls of the gate electrodes
14
. Active source and drain regions may be formed in the substrate
10
between the plurality of gate electrodes
14
using high-density ion-implantation. The gate electrodes
14
may comprise polysilicon.
FIG. 2
illustrates the formation of an insulating layer
18
on the structure shown in FIG.
1
. The insulating layer
18
may comprise an oxide layer which is formed on the entire substrate
10
as shown in FIG.
2
. As shown in
FIG. 3
an Anti-Reflective Layer (ARL)
20
is formed on the insulating layer
18
. The ARL
20
may reduce the reflection of Ultra Violet light from the insulating layer
18
during a subsequent photolithography step.
As shown in
FIG. 4
, a photoresist film
22
is formed on the ARL
20
aligned to mask the underlying active regions of the integrated circuit substrate
10
. The non-masked surfaces of the ARL
20
are exposed in a photolithography step. The formation of the photoresist film
22
may add steps to the fabrication process. In particular, additional fabrication steps may include mask alignment, mask formation and mask removal. These steps may add complexity and cost to the fabrication process.
As shown in
FIG. 5
, non-masked portions of the ARL
20
and the underlying insulating layer
18
of the structure shown in
FIG. 4
are removed via etching to expose portions of the gate electrodes
14
. The etching step forms a plurality of Silicide Blocking Layers
18
a
which include the portions of the insulating layer
18
, spacers
16
, and the ARL
20
(between the plurality of gate electrodes
14
) which were underlying the photoresist film
22
in FIG.
4
.
As shown in
FIG. 6
, the ARL
20
is removed with a wet-type cleaning process using an Hydrofluoric type etchant. Otherwise, a Silicide film applied during a subsequent step may not adhere properly to the ARL
20
which may cause failures in the integrated circuit.
As shown in
FIG. 7
, refractory metals, such as Co, Ti, and Ni, are used to form a Silicide film
24
on the gate electrodes
14
during a high temperature treatment. In particular, the materials that comprise the gate electrodes
14
react with the Silicide film
24
to form a low resistance metal contact. In the regions where the SBL
18
a
was not removed, the high temperature treatment forms non-reactive metals which are then removed from the integrated circuit.
If the photoresist film
22
is misaligned, the Silicide film
24
may form only partially on the plurality of gate electrodes
14
or may form on the active regions (such as the active source and drain regions in the integrated circuit substrate
10
). Moreover, as the integration level of the integrated circuits increases, the misalignment may worsen.
In view of the above, there continues to exist a need to further improve the fabrication of integrated circuits having contacts formed therein using Salicide processes.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to allow improvements in the fabrication of conductive lines in integrated circuit memories.
It is a further object of the present invention to allow a reduction in the number of steps to fabricate conductive lines in integrated circuit memories.
These and other objects of the present invention are provided by forming a patterned blocking layer on a substrate between a plurality of conductive lines which expose the outer surface of the conductive lines without using photolithography to form the patterned blocking layer. In particular, an electrically insulating layer is formed on a plurality of electrically conductive lines and on the substrate between the plurality of electrically conductive lines. The portion of the electrically insulating layer located on the substrate between the plurality of electrically conductive lines is etched to form the self-aligned blocking layer. A Silicide film is formed on the plurality of electrically conductive lines, but not on the self-aligned blocking layer.
According to the present invention, a mask is not used to remove the electrically insulating layer to form the blocking layer. In conventional processes, a mask may be used to create a blocking layer which may add the steps of mask alignment, mask formation on the substrate, and mask removal from the substrate to the fabrication process. Also, because the self-aligned blocking layer of the present invention is formed without a photolithographic step, an anti-reflective layer may not be needed. Moreover, conventional processes may add margin to the mask alignment step to allow for mask misalignment which may complicate the fabrication process.
In a further aspect of the invention, an etch stopping layer is formed on the plurality of conductive lines and under the electrically insulating layer. In particular, the electrically insulating layer is removed until the etch stopping layer is exposed. Subsequently, the etch stopping layer is removed from the outer surfaces of the plurality of conductive lines.
In a further aspect of the present invention, an electrically insulating layer is formed on the first and second electrically conductive lines and on a portion of the substrate between the first and second electrically conductive lines. A portion of the electrically insulating layer is removed from the substrate between the first and second electrically conductive lines, wherein a residue of the electrically insulating layer remains in contact with the substrate and is self-aligned with the first and second electrically conductive lines. First and second Silicide contacts are formed on the first and second electrically conductive lines, wherein the first and second Silicide contacts are self-aligned to the residue on the electrically insulating layer.


REFERENCES:
patent: 5589423 (1996-12-01), White et al.
patent: 6015748 (2000-01-01), Kim et al.

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