Methods of forming electrical interconnects on semiconductor sub

Details Methods of forming electrical interconnects on semiconductor sub Methods of forming electrical interconnects on semiconductor sub

1997-08-05

1999-01-26

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438574, 438579, 438605, 438652, 438598, 257 4, 257587, H01L 2128

Patent

active

058638350

ABSTRACT:
Methods of forming electrical interconnects on semiconductor substrates include the steps of forming a first electrically insulating layer (e.g., silicon dioxide) and then forming a contact hole in the insulating layer to expose a layer underlying the insulating layer. A first electrically conductive region (e.g., W, Ti, Tin, Al) is then formed in the contact hole. A step is then performed to remove a portion of the first electrically insulating layer to define a recess therein which preferably surrounds an upper portion of the first conductive region. A second electrically conductive region (e.g., Al, Cu, W, Ti, Ta and Co) is then formed in the recess. Here, the first conductive region is preferably chosen to have good step coverage capability to fully bury the contact hole and the second conductive region is preferably chosen to have very low resistance even if some degree of step coverage capability is sacrificed. Planarization steps (e.g, CMP, etch-back) may also be performed to define the first conductive region in the contact hole and define the second conductive region in the recess surrounding the first conductive region. Barrier metal layers may also be conformable deposited in the contact hole prior to forming the first conductive region therein and in the recess prior to forming the second conductive region therein.

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