Methods of forming electrical interconnect structures using...

Details Methods of forming electrical interconnect structures using... Methods of forming electrical interconnect structures using...

2006-09-12

2009-02-10

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S696000, C438S711000, C438S725000, C438S738000, C257SE21024, C257SE21025, C257SE21252, C257SE21259, C257SE21486

Reexamination Certificate

active

07488687

ABSTRACT:
Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.

REFERENCES:
patent: 4371407 (1983-02-01), Kurosawa
patent: 5942446 (1999-08-01), Chen et al.
patent: 5990007 (1999-11-01), Kajita et al.
patent: 6184142 (2001-02-01), Chung et al.
patent: 6284149 (2001-09-01), Li et al.
patent: 6524964 (2003-02-01), Yu
patent: 6593246 (2003-07-01), Hasegawa et al.
patent: 6617253 (2003-09-01), Chu et al.
patent: 6689695 (2004-02-01), Lui et al.
patent: 6740566 (2004-05-01), Lyons et al.
patent: 6793832 (2004-09-01), Saito et al.
patent: 6905800 (2005-06-01), Yuen et al.
patent: 6927178 (2005-08-01), Kim et al.
patent: 7265056 (2007-09-01), Tsai et al.
patent: 7285853 (2007-10-01), Liu
patent: 362219960 (1987-09-01), None
patent: 405102101 (1993-04-01), None
patent: 11-067909 (1999-03-01), None
patent: 2000-133638 (2000-05-01), None
patent: 2001-044189 (2001-02-01), None
patent: 2003-188253 (2003-07-01), None
patent: 2003-303811 (2003-10-01), None
patent: 2005-203429 (2005-07-01), None
patent: 1020000076668 (2000-12-01), None
patent: 1020010015338 (2001-02-01), None
patent: 2001-0080234 (2001-08-01), None
patent: 1020030001089 (2003-01-01), None
patent: 2003-0041203 (2003-05-01), None
Process for Fabrications of Shallow and Deep Silicon Dioxide FilledTrenches, IBM Technical Digest, Apr. 1, 1980.

Affiliated with

Also associated with

Rating

Methods of forming electrical interconnect structures using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming electrical interconnect structures using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming electrical interconnect structures using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4103789