Methods of forming dynamic random access memory trench...

Details Methods of forming dynamic random access memory trench... Methods of forming dynamic random access memory trench...

2004-10-15

2008-08-12

Schillinger, Laura M (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

07410861

ABSTRACT:
DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

REFERENCES:
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4569701 (1986-02-01), Oh
patent: 4604150 (1986-08-01), Lin
patent: 4649625 (1987-03-01), Lu
patent: 5089872 (1992-02-01), Ozturk et al.
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5242847 (1993-09-01), Ozturk et al.
patent: 5444302 (1995-08-01), Nakajima et al.
patent: 5662768 (1997-09-01), Rostoker
patent: 5898189 (1999-04-01), Gardner et al.
patent: 5913125 (1999-06-01), Brouillette et al.
patent: 5982005 (1999-11-01), Hidaka et al.
patent: 6069049 (2000-05-01), Geiss et al.
patent: 6180480 (2001-01-01), Economikos et al.
patent: 6191432 (2001-02-01), Sugiyama et al.
patent: 6204524 (2001-03-01), Rhodes
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6232138 (2001-05-01), Fitzgerald et al.
patent: 6235568 (2001-05-01), Murthy et al.
patent: 6258689 (2001-07-01), Bronner et al.
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6294424 (2001-09-01), Kang et al.
patent: 6326664 (2001-12-01), Chau et al.
patent: 6395597 (2002-05-01), Noble
patent: 6399976 (2002-06-01), Geiss et al.
patent: 6404003 (2002-06-01), McMillan et al.
patent: 6429470 (2002-08-01), Rhodes
patent: 6441423 (2002-08-01), Mandelman et al.
patent: 6495868 (2002-12-01), Fitzgerald et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6583000 (2003-06-01), Hsu et al.
patent: 6589335 (2003-07-01), Bulsara et al.
patent: 6594293 (2003-07-01), Bulsara et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6657223 (2003-12-01), Wang et al.
patent: 6703648 (2004-03-01), Xiang et al.
patent: 6743684 (2004-06-01), Liu
patent: 6800892 (2004-10-01), Bhattacharyya
patent: 6828211 (2004-12-01), Chi
patent: 6849508 (2005-02-01), Lochtefeld et al.
patent: 6891209 (2005-05-01), Bulsara et al.
patent: 6902965 (2005-06-01), Ge et al.
patent: 6927444 (2005-08-01), Park et al.
patent: 6936881 (2005-08-01), Yeo et al.
patent: 6940705 (2005-09-01), Yeo et al.
patent: 6982472 (2006-01-01), Kiyotoshi
patent: 7015530 (2006-03-01), Bhattacharyya
patent: 7018886 (2006-03-01), Chi
patent: 7037772 (2006-05-01), Yeo et al.
patent: 7042052 (2006-05-01), Bhattacharyya
patent: 2001/0040244 (2001-11-01), Fitzgerald et al.
patent: 2002/0030227 (2002-03-01), Bulsara et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0129762 (2002-09-01), Bulsara et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
patent: 2003/0013287 (2003-01-01), Lochtefeld et al.
patent: 2003/0017667 (2003-01-01), Park et al.
patent: 2003/0030091 (2003-02-01), Bulsara et al.
patent: 2004/0007724 (2004-01-01), Murthy et al.
patent: 2004/0014276 (2004-01-01), Murthy et al.
patent: 2004/0040493 (2004-03-01), Vineis et al.
patent: 2004/0063300 (2004-04-01), Chi
patent: 2004/0070035 (2004-04-01), Murthy et al.
patent: 2004/0084735 (2004-05-01), Murthy et al.
patent: 2004/0115916 (2004-06-01), Lochtefeld et al.
patent: 2004/0119101 (2004-06-01), Schrom et al.
patent: 2004/0142545 (2004-07-01), Ngo et al.
patent: 2004/0155317 (2004-08-01), Bhattacharyya
patent: 2004/0156225 (2004-08-01), Bhattacharyya
patent: 2004/0173815 (2004-09-01), Yeo et al.
patent: 2005/0018380 (2005-01-01), Yeo et al.
patent: 2005/0023586 (2005-02-01), Bhattacharyya
patent: 2005/0026390 (2005-02-01), Chi
patent: 2005/0035389 (2005-02-01), Bulsara et al.
patent: 2005/0059214 (2005-03-01), Cheng et al.
patent: 2005/0067647 (2005-03-01), Bulsara et al.
patent: 2005/0098774 (2005-05-01), Lochtefeld et al.
patent: 2005/0205929 (2005-09-01), Nagano et al.
patent: 2005/0208717 (2005-09-01), Yeo et al.
patent: 2005/0230732 (2005-10-01), Park et al.
patent: 2005/0247982 (2005-11-01), Bhattacharyya
patent: 2006/0024877 (2006-02-01), Mandelman et al.
patent: 2006/0121394 (2006-06-01), Chi
patent: 2006/0125010 (2006-06-01), Bhattacharyya
patent: 2006/0128107 (2006-06-01), Bhattacharyya
patent: 0 862 207 (1998-09-01), None
patent: 0 987 765 (2000-03-01), None
patent: 01/17014 (2001-03-01), None
patent: 01/54202 (2001-07-01), None
Gannavaram, et al., “Low Temperature (≦800° C) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS,”IEEE International Electron Device Meeting Technical Digest, (2000), pp. 137-440.
Ge et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,”IEEE International Electron Devices Meeting Technical Digest, (2003) pp. 73-76.
Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,”IEEE International Electron Devices Meeting Technical Digest, (2003), 11.6.1-11.6.3.
Hamada et al., “A New Aspect of Mechanical Stress Effects in Scaled MOC Devices,”IEEE Transactions on Electron Devices, vol. 38, No. 4 (Apr. 1991), pp. 895-900.
Huang et al., “Isolation Process Dependence of Channel Mobility in Thin-Film SOI Devices,”IEEE Electron Device Letters, vol. 17, No. 6 (Jun. 1996), pp. 291-293.
Huang et al., “LOCOS-Induced Stress Effects on Thin-Film SOI Devices,”IEEE Transactions on Electron Devices, vol. 44, No. 4 (Apr. 1997), pp. 646-650.
Huang, et al., “Reduction of Source/Drain Series Resistance and Its Impact on Device Performance for PMOS Transistors with Raised Si1-xGexSource/Drain”,IEEE Electron Device Letters, vol. 21, No. 9, (Sep. 2000) pp. 448-450.
Iida et al., “Thermal behavior of residual strain in silicon-on-insulator bonded wafer and effects on electron mobility,”Solid-State Electronics, vol. 43 (1999), pp. 1117-1120.
Ito et al., “Mechanical Stress Effect on Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design,”IEEE International Electron Devices Meeting Technical Digest, (2000), pp. 247-250.
Lochtefeld et al., “Investigating the Relationship Between Electron Mobility and Velocity in Deeply Scaled NMOS via Mechanical Stress,”IEEE Electron Device Letters, vol. 22, No. 12 (2001), pp. 591-593.
Ootsuka et al., “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications,”IEEE International Electron Devices Meeting Technical Digest, (2000), pp. 575-578.
Ota et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,”IEEE International Electron Devices Meeting Technical Digest, (2002), pp. 27-30.
Öztürk, et al., “Advanced Si1-xGexSource/Drain and Contact Technologies for Sub-70 nm CMOS,”IEEE International Electron Device Meeting Technical Digest, (2002), pp. 375-378.
Öztürk, et al., “Ultra-Shallow Source/Drain Junctions for Nanoscale CMOS Using Selective Silicon-Germanium Technology,”Extended Abstracts of International Workshop on Junction Technology, (2001), pp. 77-82.
Öztürk, et al., “Selective Silicon-Gremanium Source/Drain Technology for Nanoscale CMOS,”Mat. Res. Soc. Symp. Proc., vol. 717, (2002), pp. C4.1.1-C4.1.12.
Öztürk, et al., “Low Resistivity Nickel Germanosilicide Contacts to Ultra-Shallow Si1-xGexSource/Drain Junctions for Nanoscale CMOS,”IEEE International Electron Device Meeting Technical Digest(2003), pp. 497-500.
Shimizu et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,”IEEE International Electron Devices Meeting Technical Digest, (2001), pp. 433-436.
Thompson et al., “A Logic Nanotechnology Featuring Strained-Silicon,”IEEE Electron Device Letters, vol. 25, No. 4 (Apr. 2004), pp. 191-193.
Thompson et al., “A 90 nm Logic Technology Featuring 50nm Strained-Silicon Channel Transistors, 7 layers of CuInterconnects, Low k ILD, and l um2SRAM Cell,”IEEE International Electron Devices Meeting Technical Digest, (2002), pp. 61-64.
Tiwari et al., “Hole Mo

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