Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-12-04
2011-10-04
Coleman, William D (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21035, C438S723000
Reexamination Certificate
active
08030156
ABSTRACT:
Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.
REFERENCES:
patent: 4028155 (1977-06-01), Jacob
patent: 6620737 (2003-09-01), Saito et al.
patent: 7256120 (2007-08-01), Tsao et al.
patent: 7335611 (2008-02-01), Ramaswamy et al.
patent: 7344996 (2008-03-01), Lang et al.
patent: 2003/0148581 (2003-08-01), Kim et al.
patent: 2003/0148858 (2003-08-01), Kim et al.
patent: 2006/0134921 (2006-06-01), Wu et al.
patent: 2007/0131652 (2007-06-01), Okune et al.
patent: 2007/0197033 (2007-08-01), Wilson
patent: 0596593 (1994-11-01), None
patent: 1498941 (2005-01-01), None
patent: 2000-223478 (2000-08-01), None
patent: PCT/US2007/023391 (2008-04-01), None
patent: PCT/US2007/023391 (2009-06-01), None
Coleman William D
Micro)n Technology, Inc.
Wells St. John P.S.
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