Methods of forming contacts, methods of contacting lines,...

Details Methods of forming contacts, methods of contacting lines,... Methods of forming contacts, methods of contacting lines,...

1998-09-02

2002-04-30

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S142000, C438S233000, C438S381000, C438S586000, C438S597000, C438S598000

Reexamination Certificate

active

06380023

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming contacts, to methods of contacting lines, and to methods of operating integrated circuitry. The invention also relates to integrated circuits.
BACKGROUND OF THE INVENTION
Conductive lines which are utilized in integrated circuitry are often formed with widened areas called contact or landing pads. The purpose of these pads is to provide an extra degree of protection should a misalignment occur between a contact opening which is formed over the line. While advantages are gained in reducing the chances of a misalignment-induced failure, valuable wafer real estate is consumed by the widened pads.
Referring to
FIG. 1
, a portion of an exemplary prior art layout is shown generally at
10
and includes conductive lines
12
,
14
and
16
having widened contact pads
18
,
20
and
22
, respectively. To conserve wafer real estate, it is usually desirable to provide conductive lines
12
,
14
,
16
to have a minimum pitch which is defined in large part by the minimum photolithographic feature size used to fabricate the circuitry. Minimizing the pitch of the lines ensures that the space between the lines, represented at S, is as small as possible. Yet, to ensure that subsequently formed contacts to the conductive lines do not short to the substrate, the above-described widened contact pads are used. A design trade-off, however, is that in order to maintain a desired pitch between the conductive lines, and to avoid forming the contact pads too close together, the contact pads must necessarily be moved outwardly of one another. For example, in
FIG. 1
, contact pad
18
is moved outward in the direction of arrow A. Other contact pads can be spaced even further out depending on the dimensions of the contact pads. This results in consumption of valuable wafer real estate.
SUMMARY OF THE INVENTION
Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.


REFERENCES:
patent: 4281448 (1981-08-01), Barry et al.
patent: 4936928 (1990-06-01), Shaw et al.
patent: 5162890 (1992-11-01), Butler
patent: 5166096 (1992-11-01), Cote et al.
patent: 5173752 (1992-12-01), Motonami et al.
patent: 5206187 (1993-04-01), Doan et al.
patent: 5243219 (1993-09-01), Katayama
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5317193 (1994-05-01), Watanabe
patent: 5444003 (1995-08-01), Wang et al.
patent: 5510648 (1996-04-01), Davies et al.
patent: 5547892 (1996-08-01), Wuu et al.
patent: 5552620 (1996-09-01), Lu et al.
patent: 5576243 (1996-11-01), Wuu et al.
patent: 5591662 (1997-01-01), Zambrano
patent: 5600170 (1997-02-01), Sugiyama et al.
patent: 5612240 (1997-03-01), Chang et al.
patent: 5652174 (1997-07-01), Wuu et al.
patent: 5668021 (1997-09-01), Subramanian et al.
patent: 5686331 (1997-11-01), Song
patent: 5707883 (1998-01-01), Tabara
patent: 5710450 (1998-01-01), Chau et al.
patent: 5731610 (1998-03-01), Rhodes
patent: 5736441 (1998-04-01), Chen
patent: 5747359 (1998-05-01), Yuan et al.
patent: 5763321 (1998-06-01), Ohshima et al.
patent: 5808320 (1998-09-01), Dennison
patent: 5811350 (1998-09-01), Dennison
patent: 5814886 (1998-09-01), Mano
patent: 5827770 (1998-10-01), Rhodes
patent: 5858832 (1999-01-01), Pan
patent: 5864155 (1999-01-01), Melzner
patent: 5874359 (1999-02-01), Liaw et al.
patent: 5885890 (1999-03-01), Dennison
patent: 5891780 (1999-04-01), Hasegawa et al.
patent: 5895269 (1999-04-01), Wang et al.
patent: 5897350 (1999-04-01), Lee et al.
patent: 5899712 (1999-05-01), Choi et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5930618 (1999-07-01), Sun et al.
patent: 5946578 (1999-08-01), Fujii
patent: 5960318 (1999-09-01), Peschke et al.
patent: 5970360 (1999-10-01), Cheng et al.
patent: 5990524 (1999-11-01), En et al.
patent: 6093609 (2000-07-01), Chuang et al.
patent: 6097103 (2000-08-01), Ishigaki
patent: 6133103 (2000-10-01), Lee et al.
Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Third Edition, 1993, John Wiley and Sons, p. 169—specifically the 2nd paragraph.*
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 3: The Submicron MOSFET, Lattice Press, p. 136-138, 232-234, 1995.*
Shenai, K., “A high-density, self-aligned power MOSFET structure fabricated using sacrificial spacer technology” Electron Devices, IEEE Transactions on Electron Devices, vol. 39, Issue 5, May 1992, pp. 1252-1255.
Wolf, S., “Silicon Processing for the VLSI Era,” vol. 3: The Submicron MOSFET, Lattice Press 1995, pp. 634-636.

Affiliated with

Also associated with

Rating

Methods of forming contacts, methods of contacting lines,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of forming contacts, methods of contacting lines,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming contacts, methods of contacting lines,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2893557