Methods of forming CMOS integrated circuit devices and...

Details Methods of forming CMOS integrated circuit devices and... Methods of forming CMOS integrated circuit devices and...

2007-03-27

2007-03-27

Owens, Douglas W. (Department: 2811)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S455000, C438S459000

Reexamination Certificate

active

11141275

ABSTRACT:
CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGexlayer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGexlayer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGexlayer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGexlayer varies from the peak level where 0.2<x<0.4 to a level where x=0 at the first junction. The Si1-xGexlayer also has a retrograded arsenic doping profile therein relative to the surface. This retrograded profile may result in the Si1-xGexlayer having a greater concentration of first conductivity type dopants therein relative to the concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. The total amount of dopants in the channel region and underlying Si1-xGexlayer can also be carefully controlled to achieve a desired threshold voltage.

REFERENCES:
patent: 5166084 (1992-11-01), Pfiester
patent: 5218213 (1993-06-01), Gaul et al.
patent: 5240876 (1993-08-01), Gaul et al.
patent: 5310451 (1994-05-01), Tejwani et al.
patent: 5378923 (1995-01-01), Mitsui et al.
patent: 5461243 (1995-10-01), Ek et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5527724 (1996-06-01), Brady et al.
patent: 5583059 (1996-12-01), Burghartz
patent: 5650340 (1997-07-01), Burr et al.
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5726459 (1998-03-01), Hsu et al.
patent: 5759898 (1998-06-01), Ek et al.
patent: 5767549 (1998-06-01), Chen et al.
patent: 5773328 (1998-06-01), Blanchard
patent: 5814854 (1998-09-01), Liu et al.
patent: 5847419 (1998-12-01), Imai et al.
patent: 5882967 (1999-03-01), Brown et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5891769 (1999-04-01), Liaw et al.
patent: 5906951 (1999-05-01), Chu et al.
patent: 5930643 (1999-07-01), Sadana et al.
patent: 5939767 (1999-08-01), Brown et al.
patent: 5962892 (1999-10-01), Takeuchi
patent: 5963817 (1999-10-01), Chu et al.
patent: 6033974 (2000-03-01), Henley et al.
patent: 6048756 (2000-04-01), Lee et al.
patent: 6049110 (2000-04-01), Koh
patent: 6051509 (2000-04-01), Tsuchiaki
patent: 6059895 (2000-05-01), Chu et al.
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6124614 (2000-09-01), Ryum et al.
patent: 6124627 (2000-09-01), Rodder et al.
patent: 6287926 (2001-09-01), Hu et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6633066 (2003-10-01), Bae et al.
patent: 9-321307 (1997-12-01), None
patent: WO 97/23000 (1997-06-01), None
Alieu et al., “Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 130-131.
Mizuno et al., “High Performance Strained-Si p-MOSFET on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology,” 1999 IEEE, IEDM, pp. 934-936.
Sim et al., “Elimination of Parasitic Bipolar-Induced Breakdown Effects in Ultra-Thin SOI MOSFET's Using Narrow-Bandgap-Source (NBS) Structure,” IEEE Transactions on Electron Devices, vol. 42, No. 8, Aug. 1995, pp. 1495-1502.
Yoshimi et al., “Suppression of the Floating-Body Effect in SOI MOSFET's by the Bandgap Engineering Method Using a Si1-χGeχSource Structure,” IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, pp. 423-429.

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