Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-15
2003-09-16
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S255000, C438S398000, C438S734000
Reexamination Certificate
active
06620686
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-7308, filed Feb. 16, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit capacitors and, more particularly, to integrated circuit capacitors having hemispherical grain (HSG) nodules disposed on a silicon electrode.
BACKGROUND OF THE INVENTION
As the integration density of semiconductor devices, such as dynamic random access memory (DRAM) devices, increases, the area that is allocated to capacitors that comprise memory cells in a DRAM may be reduced. Various methodologies may be used to form a capacitor having a high capacitance in a reduced area, such as thinning the dielectric film, using a dielectric film having a high dielectric constant, and/or increasing the surface area of the capacitor electrodes. The surface area of capacitor electrodes may be increased by forming the electrodes in a three-dimensional structure, such as a cylindrical shape or fin shape, and/or by growing hemispherical grain (HSG) nodules or asperities on the surface of the capacitor electrodes. Exemplary structures of HSG capacitors and/or methods of forming same are described in U.S. Pat. No. 6,087,226 to Kim et al., U.S. Pat. No. 6,077,573 to Kim et al., U.S. Pat. No. 6,004,858 to Shim et al., U.S. Pat. No. 5,960,281 to Nam et al., U.S. Pat. No. 5,943,570 to Park et al., U.S. Pat. No. 5,885,867 to Shin et al., U.S. Pat. No. 5,821,152 to Han et al., and U.S. Pat. No. 5,597,756 to Fazan et al., the disclosures of which are hereby incorporated herein by reference.
A lower electrode
10
of a conventional HSG capacitor is illustrated in
FIG. 1
where it may be seen that the HSG nodules grown thereon provide increased surface area as compared to a cylindrical electrode without HSG nodules grown thereon. The increased surface area of the lower electrode
10
may increase the capacitance of a capacitor incorporating the lower electrode
10
. A substrate undergoing a HSG growth process, which is generally a single wafer type process, may then be moved to a batch type dielectric deposition chamber. During the transfer to the dielectric deposition chamber, a wafer may be exposed to the atmosphere, which may result in the formation and/or absorption of native oxide layers and/or contaminant particles on/in the surface of the wafer. Accordingly, a cleaning process is typically performed to remove the native oxide layers or contaminants from the surface of the wafer before deposition of a dielectric film. Unfortunately, a portion
12
of the lower electrode
10
may separate from the electrode
10
during the cleaning process and may attach to another lower electrode that is adjacent the lower electrode
10
. Moreover, the portion
12
may create an electrical bridge between the lower electrode
10
and an adjacent lower electrode, which may make it difficult to electrically distinguish between two memory cells in which the storing and/or reading of data is performed independently of each other. In view of the foregoing, there exists a need for improved HSG capacitors and methods of forming same.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a capacitor includes an electrode that has an inner surface, an outer surface, and an end surface. At least one of the inner surface and the outer surface has hemispherical grain (HSG) nodules thereon, but the end surface is substantially devoid of HSG nodules. By maintaining the end surface of the electrode substantially devoid of HSG nodules, the mechanical strength and integrity of the end surface may not be degraded. Therefore, the frequency in which portions of the end surface break away during, for example, a cleaning process, and create electrical bridges with adjacent electrodes may be reduced. The present invention stems from a realization that HSG nodule growth may be suppressed by performing a plasma treatment using a C
x
H
y
F
z
-series gas on the end surface of the electrode so as to form a polymer layer thereon.
In further embodiments of the present invention, an HSG capacitor is formed via the following steps: An inter-electrode insulating pattern is formed and a trench is etched therein. A silicon layer is formed on the inter-electrode insulating pattern and in the trench. The silicon layer may serve as an electrode of the capacitor and has an inner and outer surface. An insulating layer is formed on the silicon layer and then the insulating layer, the silicon layer, and the inter-electrode insulating pattern are planarized, via, for example, chemical mechanical polishing or a dry etch-back process using a C
x
F
y
-series gas, so as to form and expose an end surface of the silicon layer. A polymer layer is formed on the exposed end surface of the silicon layer. One or both of the insulating layer and the inter-electrode insulating pattern are then removed and HSG nodules are formed on either or both of the inner and outer surfaces of the silicon layer. After formation of the HSG nodules on the silicon layer, a dielectric film and another electrode may be formed on the silicon layer to complete the formation of a capacitor.
The silicon layer may be deposited amorphously on the inter-electrode insulating pattern by chemical vapor deposition (CVD) and may also be doped with impurities during the deposition process. The impurities may include phosphorous and/or arsenic ions and their concentration may be substantially uniform throughout the silicon layer or their concentration may be non-uniform in the silicon layer. The doping concentration of impurities in the silicon layer may affect the average size of HSG nodules formed thereon. Thus, by varying the doping concentration of impurities between the inner surface of the silicon layer and the outer surface of the silicon layer, the average size of HSG nodules formed on the inner and outer surfaces of the silicon layer may be made to differ in accordance with the needs of particular applications.
The polymer layer may be formed both on the end surface of the silicon layer and on adjacent corners of the silicon layer, which are defined by the intersection of the end surface with the inner and outer surfaces of the silicon layer. To form the polymer layer, a plasma treatment may be applied to the insulating layer, the end surface of the silicon layer, and the inter-electrode insulating pattern so as to etch the insulating layer and the inter-electrode insulating pattern. Preferably, the plasma comprises a C
x
H
y
F
z
-series gas, such as CHF
3
or CH
2
F
2
.
Thus, in summary, embodiments of the present invention provide HSG capacitors and methods of forming same in which a portion of an electrode is maintained as substantially devoid of HSG nodules through use of a polymer layer formed on that portion. By suppressing growth of HSG nodules on a portion of the electrode, the mechanical strength and integrity of that portion may be maintained, which may reduce the frequency in which that portion may break loose from the electrode to form an electrical bridge with an adjacent electrode.
REFERENCES:
patent: 5597756 (1997-01-01), Fazan et al.
patent: 5821152 (1998-10-01), Han et al.
patent: 5895867 (1999-03-01), Shin et al.
patent: 5933727 (1999-08-01), Figura
patent: 5943570 (1999-08-01), Park et al.
patent: 5960281 (1999-09-01), Nam et al.
patent: 6004858 (1999-12-01), Shim et al.
patent: 6077573 (2000-06-01), Kim et al.
patent: 6087226 (2000-07-01), Kim et al.
patent: 6177309 (2001-01-01), Lee
patent: 6180451 (2001-01-01), Hsieh et al.
patent: 6326277 (2001-12-01), DeBoer
patent: 6440869 (2002-08-01), Tseng
patent: 2001-0001164 (2001-01-01), None
Notice to Submit Response, Korean Application No. 10-2000-0007308, Dec. 21, 2001.
Hwang Ki-hyun
Kim Dong-hyun
Le Vu A.
Luu Pho M.
Myers Bigel Sibley & Sajovec P.A.
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