Methods of forming capacitors, and methods of forming DRAM...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S387000, C257SE21647, C257SE29001

Reexamination Certificate

active

07829410

ABSTRACT:
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

REFERENCES:
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5595928 (1997-01-01), Lu et al.
patent: 5650351 (1997-07-01), Wu
patent: 5663093 (1997-09-01), Tseng et al.
patent: 5783462 (1998-07-01), Huang
patent: 5962885 (1999-10-01), Fischer et al.
patent: 6190964 (2001-02-01), Winters
patent: 6204143 (2001-03-01), Roberts et al.
patent: 6251726 (2001-06-01), Huang
patent: 6362043 (2002-03-01), Noble
patent: 6791135 (2004-09-01), Takenaka
patent: 7112487 (2006-09-01), Gutsche et al.
patent: 7112840 (2006-09-01), Kim et al.
patent: 7271051 (2007-09-01), Manning et al.
patent: 7315466 (2008-01-01), Han et al.
patent: 7489564 (2009-02-01), Keeth et al.
patent: 2002/0050606 (2002-05-01), Buerger, Jr.
patent: 2004/0016957 (2004-01-01), Wu
patent: 2006/0202250 (2006-09-01), Hecht et al.
patent: 2006/0211178 (2006-09-01), Kim et al.
patent: 2006/0261396 (2006-11-01), Joo
patent: 2007/0001208 (2007-01-01), Graham et al.
patent: 2007/0117340 (2007-05-01), Steltenpohl
patent: 2007/0232013 (2007-10-01), Manning et al.
patent: 2007/0235786 (2007-10-01), Kapteyn et al.
patent: 2321769 (1998-08-01), None
patent: 10200713072 (2007-01-01), None
patent: PCT/US2008/080196 (2006-06-01), None
patent: PCT/US2008/080196 (2009-06-01), None
Kim, D.H. et al. “A Mechanically Enhanced Storage node for virtually unlimited Height (MESH) Capacitor Aiming at sub 70nm DRAMs” IEEE Jan. 2004; pp. 3.4.1-3.4.4.
Sim, S.P., et al. “A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs” IEEE © 1996 pp. 22.3.1-22.3.4.
Nemati, Farid “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device” 1998 Symposium on VLSI Technology Digest of Technical Papers, Jun. 1998 pp. 66-67.
Horii, Hideki, et al. “A Self-aligned Stacked Capacitor using Novel Pt Electroplating Method for 1 Gbit DRAMs and Beyond” 1999 Symposium on VLSI Technology Digest of Technical Papers; pp. 103-104.

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