Methods of forming capacitors and DRAM arrays

Details Methods of forming capacitors and DRAM arrays Methods of forming capacitors and DRAM arrays

1997-02-11

1999-11-09

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, H01L 218242

Patent

active

059813334

ABSTRACT:
The invention encompasses methods of forming DRAM constructions, methods of forming capacitor constructions, DRAM constructions, and capacitor constructions. The invention includes a method in which a) a first layer is formed over a node location; b) a semiconductive material masking layer is formed over the first layer; c) an opening is formed through the semiconductive material masking layer and the first layer to the node location; d) an upwardly open capacitor storage node layer is formed within the opening; e) a storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and a capacitor plate are formed over the storage node. The invention also includes a capacitor structure comprising: a) an insulative layer over a substrate; b) a polysilicon layer over the insulative layer; c) an opening extending through the polysilicon layer and the insulative layer to a node, the opening comprising an upper portion and a lower portion, the upper portion comprising a first minimum cross-sectional dimension and the lower portion comprising a second minimum cross-sectional dimension which is narrower than the first minimum cross-sectional dimension, the opening further comprising a step at an interface of the upper and lower portions; d) a spacer over the step; e) a storage node layer over the spacer, polysilicon layer and the node; and f) a dielectric layer and a cell plate layer capacitively coupled to the storage node layer.

REFERENCES:
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4864374 (1989-09-01), Banerjee
patent: 5170233 (1992-12-01), Liu et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5227325 (1993-07-01), Gonzalez
patent: 5229310 (1993-07-01), Sivan
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5244826 (1993-09-01), Gonzalez et al.
patent: 5270968 (1993-12-01), Kim et al.
patent: 5283455 (1994-02-01), Inoue et al.
patent: 5323038 (1994-06-01), Gonzalez et al.
patent: 5334862 (1994-08-01), Manning et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5385858 (1995-01-01), Manabe
patent: 5401681 (1995-03-01), Dennison
patent: 5444013 (1995-08-01), Akram et al.
patent: 5482886 (1996-01-01), Park et al.
patent: 5543345 (1996-08-01), Liaw et al.
patent: 5700731 (1997-12-01), Lin et al.
Hayden, J.D., et. al., "A New Toroidal TFT Structure For Future Generation SRAMs", IEEE 1993, pp. 825-828, IEDM.
Sakao, M., "A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical-Grain Storage Node For 64Mb DRAMs", 1990 IEEE, pp. 27.3.1-27.3.4.
Aoki, M., et. al., "Fully Self-Aligned 6F.sup.2 Cell Technology For Low Cost 1Gb DRAM", 1996 IEEE, pp. 22-23.
IBM Technical Disclosure Bulletin, "Methods of Forming Small Contact Holes", vol. 30, No. 8 (Jan. 1988), pp. 252-253.

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