Methods of forming capacitor structures and DRAM arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S254000, C438S255000, C438S396000, C438S397000, C438S398000, C438S719000, C438S739000, C438S753000, C438S964000

Reexamination Certificate

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06864138

ABSTRACT:
The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

REFERENCES:
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4864374 (1989-09-01), Banerjee
patent: 5049517 (1991-09-01), Liu et al.
patent: 5170233 (1992-12-01), Liu et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5227325 (1993-07-01), Gonzalez
patent: 5229310 (1993-07-01), Sivan
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5244826 (1993-09-01), Gonzalez et al.
patent: 5270968 (1993-12-01), Kim et al.
patent: 5283455 (1994-02-01), Inoue et al.
patent: 5294561 (1994-03-01), Tanigawa
patent: 5318927 (1994-06-01), Sandhu et al.
patent: 5323038 (1994-06-01), Gonzalez et al.
patent: 5334862 (1994-08-01), Manning et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5385858 (1995-01-01), Manabe
patent: 5389560 (1995-02-01), Park
patent: 5391511 (1995-02-01), Doan et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5444013 (1995-08-01), Akram et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 5468670 (1995-11-01), Ryou
patent: 5478768 (1995-12-01), Iwasa
patent: 5482886 (1996-01-01), Park et al.
patent: 5492848 (1996-02-01), Lur et al.
patent: 5492850 (1996-02-01), Ryou
patent: 5516719 (1996-05-01), Ryou
patent: 5550080 (1996-08-01), Kim
patent: 5554557 (1996-09-01), Koh
patent: 5563089 (1996-10-01), Jost et al.
patent: 5567640 (1996-10-01), Tseng
patent: 5604147 (1997-02-01), Fischer et al.
patent: 5605857 (1997-02-01), Jost et al.
patent: 5650351 (1997-07-01), Wu
patent: 5661064 (1997-08-01), Figura et al.
patent: 5786249 (1998-07-01), Dennison
patent: 5851898 (1998-12-01), Hsia et al.
patent: 5909616 (1999-06-01), Dennison
patent: 5918122 (1999-06-01), Parekh et al.
patent: 5953609 (1999-09-01), Koyama et al.
patent: 5981333 (1999-11-01), Parekh et al.
patent: 6027967 (2000-02-01), Parekh et al.
patent: 6060352 (2000-05-01), Sekiguchi et al.
patent: 6066541 (2000-05-01), Hsieh et al.
patent: 6083831 (2000-07-01), Dennison
patent: 6090663 (2000-07-01), Wu
patent: 6218237 (2001-04-01), Sandhu et al.
patent: 6251725 (2001-06-01), Chiou et al.
patent: 6359302 (2002-03-01), Parekh et al.
patent: 6376301 (2002-04-01), Parekh et al.
patent: 6410423 (2002-06-01), Anezaki et al.
Sakao, M., “A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical-Grain Storage Node For 64Mb DRAMs”, 1990 IEEE, pp. 27.3.1-27.3.4.
Aoki, M., et al., “Fully Self-Aligned 6F2Cell Technology For Low Cost 1Gb DRAM”, 1996 IEEE, pp. 22-23.
IBM Technical Disclosure Bulletin, “Methods of Forming Small Contact Holes”, vol. 30, No. 8 (Jan. 1988). pp. 252-253.
Hayden, J.D., et al., “A New Toroidal TFT Structure For Future Generation SRAMs”. IEEE 1993, pp. 825-828, IEDM.

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