Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-02-21
2004-01-27
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S445000
Reexamination Certificate
active
06682987
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-24884, filed May 8, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to methods of forming integrated circuit devices and integrated circuit devices formed thereby and, more particularly, to trench isolation methods and integrated circuit devices formed thereby.
BACKGROUND OF THE INVENTION
As the integration density of semiconductor devices increases, distances between devices may decrease. Accordingly, trench isolation methods may be used to isolate fine sized devices that may not be possible to isolate by conventional local oxidation of silicon (LOCOS) isolation methods. In general, trench isolation methods isolate devices by forming a trench in a semiconductor substrate and filling the trench with an insulating material, such as silicon oxide.
Unfortunately, some trench isolation methods may result in stress being concentrated on the lower part or upper corners of the trench. In addition, heat treatment and oxidization processes for densifying the material burying the trench may impose stress on a silicon substrate. Such stress may cause silicon lattice defects, such as dislocation of a silicon lattice or stacking faults, and may degrade the characteristics of semiconductor devices formed on the silicon substrate.
A conventional method for reducing the effects of stress on a silicon substrate involves forming a thin liner layer of silicon nitride in a trench before filling the trench with an insulating material. This method will be described in more detail with reference to
FIGS. 1-3
. As illustrated in
FIG. 1
, a pad oxide layer
12
and a nitride layer
14
are sequentially formed on a silicon substrate
10
and are patterned to form a mask used to etch a trench. Next, the silicon substrate
10
is etched through the mask to form a trench at a predetermined depth. An oxide layer
16
is thinly formed to cover the inner wall of the trench. A liner layer
20
comprising silicon nitride is thinly formed on the surface of the silicon substrate
10
, and a silicon oxide layer
30
is deposited on the surface of the silicon substrate
10
so as to fill the trench.
Referring now to
FIG. 2
, if a planarization process is performed to remove the silicon oxide layer
30
and nitride layer
14
on the pad oxide layer
12
and form the silicon oxide layer
32
, then the liner layer
20
may also be etched to form the liner layer
22
. As shown in
FIG. 2
, the liner layer
22
may be over etched to a predetermined depth that is slightly below the top surface of the silicon substrate
10
.
Referring now to
FIG. 3
, if the pad oxide layer
12
is etched, then the oxide layer
16
and the oxide layer
32
may also be etched to form oxide layers
17
and
32
, which remain adjacent to the liner layer
22
. Unfortunately, in region A, a dent or a groove may be generated below the surface of the silicon substrate
10
. Once a dent or a groove is generated, the depth and width of the dent or groove may increase due to subsequent ion insertion and/or cleaning process. The dent or groove may cause electrical defects, such as a hump phenomenon, decrease threshold voltage levels, and/or cause a bridge to form between gate electrodes in a semiconductor device, such as a transistor to be subsequently formed.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a trench isolation region is formed in a substrate by forming a trench-etching mask on the substrate. A trench is formed by etching the substrate through the trench-etching mask. An oxide layer is formed on sidewall and bottom surfaces of the trench. A liner layer is formed on the trench-etching mask and on the oxide layer. The liner layer is then removed at a boundary between the trench etching mask and the oxide layer so as to separate the liner layer into a first liner layer disposed on the trench etching mask and a second liner layer disposed on the oxide layer.
In other embodiments of the present invention, the liner layer is also removed at an upper surface of the trench-etching mask, opposite the substrate, and at the bottom surface of the trench.
In still other embodiments of the present invention, the liner layer comprises silicon nitride and is removed by dry etching the liner layer using an etching gas comprising at least one of Ar/CH
3
and Ar/CF
4
/O
2
. The liner layer may be formed using low-pressure chemical vapor deposition to a thickness of about 40-200 Å.
In still other embodiments of the present invention, the trench-etching mask is formed by forming a pad oxide layer on the substrate and forming a silicon nitride layer on the pad oxide layer. The pad oxide layer may be formed using thermal oxidation to a thickness of about 100-200 Å. The silicon nitride layer may be formed using low-pressure chemical vapor deposition to a thickness of about 500-1000 Å.
In still other embodiments of the present invention, forming the trench isolation region further comprises forming a trench isolation layer on the first and second liner layers and on the trench etching mask to bury the trench. The trench isolation layer is removed from an upper surface of the trench-etching mask, opposite the substrate, and from the second liner layer. The second liner layer and the trench-etching mask are then removed to expose the substrate.
In still other embodiments of the present invention, the trench isolation layer comprises high density plasma oxide and may be formed using plasma enhanced chemical vapor deposition to a thickness of about 5000-6000 Å.
REFERENCES:
patent: 6258692 (2001-07-01), Chu et al.
patent: 6391784 (2002-05-01), Ibok
patent: 2002/0014677 (2002-02-01), Han et al.
Myers Bigel Sibley & Sajovec P.A.
Perkins Pamela E.
Zarabian Amir
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