Non-volatile semiconductor memory device and semiconductor...

Details Non-volatile semiconductor memory device and semiconductor... Non-volatile semiconductor memory device and semiconductor...

2002-03-26

2004-01-06

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S318000

Reexamination Certificate

active

06674119

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No.2001-201055 filed on Jul. 2, 2001, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices. Especially it is related to a non-volatile semiconductor memory device.
A non-volatile semiconductor memory device is a semiconductor memory device capable of holding information over long time period even if the supply of electric power is turned off. EEPROMs and flash memory devices are typical examples.
In these semiconductor memory devices, information is held in a floating gate electrode in the form of electric charges. Especially, as for a flash memory device, the cell area is small and it is suited to construct a large scale integrated circuit together with other semiconductor devices, especially logic semiconductor devices.
A typical conventional flash memory device has the floating gate electrode formed on a channel region via an intervening tunneling oxide film. Furthermore, a control electrode is formed on the floating gate electrode via an insulation film.
However, the flash memory device having such a stacked electrode structure has a problem in that the fabrication process thereof is complex.
On the other hand, a flash memory device having a single-layer gate structure is proposed in a related art of the present invention.
FIG. 1A
is a plan view showing the construction of a flash memory device
10
according to such a related art, while
FIGS. 1B and 1C
show the cross-sectional view taken along a A-A′ line and B-B′ line of FIG.
1
A.
Referring to
FIGS. 1A-1C
, an active region
11
A is defined by a field oxide film
11
F formed on a Si substrate
11
, and another active region
11
B including a buried diffusion region
11
Bu is defined in the vicinity of the active region
11
A so as to extend parallel to the active region
11
A. Further, diffusion regions
11
a
and
11
b
of n+-type are formed inside the active region
11
A as shown in the cross-sectional view of FIG.
1
B.
On the Si substrate
11
, a gate electrode
13
G is formed via a gate oxide film
12
G at the part located between the diffusion regions
11
a
and
11
b.
By providing the gate electrode
13
G, there is formed a MOS transistor having a channel region between the diffusion regions
11
a
and
11
b
in the active region
11
A. This MOS transistor is used for reading the information.
Furthermore a different n+-type diffusion region
11
c
is formed in the vicinity of the diffusion region
11
b
inside the active region
11
A at the opposite side of the diffusion region
11
a,
as shown in the cross-sectional view of FIG.
1
B. Between the diffusion regions
11
b
and
11
c,
there is formed a floating gate electrode
13
FG via a tunneling oxide film
12
Tox. Further, an LDD region
11
d
of n-type is formed in a part of the diffusion region
11
b
at the side facing to the diffusion region
11
c.
Referring to the cross-sectional view of
FIG. 1C
, the floating gate electrode
13
FG on the gate oxide film
12
G extends over the field oxide film
11
F toward the active region
11
B, wherein the floating gate electrode
13
FG extends further over the gate oxide film
12
G covering the surface of Si substrate
11
in the active region
11
B.
FIGS. 2A and 2B
show the writing operation of the flash memory device
10
of
FIGS. 1A-1C
.
Referring to
FIGS. 2A and 2B
, the diffusion region
11
b
is grounded and a positive voltage of +5-+10V is applied to the diffusion region
11
c
at the time of writing. Thereby, hot electrons are formed in the vicinity of the diffusion region
11
c.
Simultaneously, a positive writing voltage of +15-20V is applied to the buried diffusion region
12
Bu in the active region
11
B. With this, the potential of the floating gate electrode
13
Fg, which is capacitance-coupled to the buried diffusion region
12
Bu, is lowered via the gate insulation film
12
G. As a result, there occurs injection of the hot electrons into the floating gate electrode
13
Fg in the active region
11
A, and the electrons thus injected are held stability in the floating gate electrode
13
Fg.
FIGS. 3A and 3B
show the erasing operation of flash memory device
10
of
FIGS. 1A-1C
.
Referring to
FIGS. 3A and 3B
, the diffusion region
11
c
is set to a floating state at the time of the erasing operation of the flash memory device and a positive erasing voltage of +15-+20V is applied to the diffusion region
11
b.
As a result, the potential of the diffusion region
11
b
is lowered and the electrons accumulated in the floating gate electrode
13
Fg are pulled out to the diffusion regions
11
d
and
11
b
through the tunneling insulation film
12
Tox.
Thus, the flash memory device
10
of
FIGS. 1A-1C
has a desirable characteristic in that the production of the device is easy due to the single-layer structure of the gate electrode.
On the other hand, as will be understood from the plane view of
FIG. 1A
, the flash memory device
10
has a problem in that the memory cell area tends to become large due to the use of two gate electrodes, the selection gate electrode
13
G and the floating gate electrode
13
Fg, at the time of reading.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and the fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a flash memory device of single-layer gate structure that can reduce the memory cell area.
Another object of the present invention is to provide a non-volatile semiconductor memory device, comprising:
a p-type Si substrate;
an n-type well formed in said Si substrate;
a control gate formed of a p-type buried diffusion region formed in said n-type well;
an active region formed in said Si substrate in the vicinity of said n-type well, said active region being covered by a tunneling insulation film; and
a floating gate electrode formed on a surface of said Si substrate so as to achieve a capacitance coupling with said p-type buried diffusion region,
said floating gate electrode extending over said active region in a state that said tunneling insulation film is interposed between said floating gate electrode and said surface of said Si substrate,
said active region including a pair of n-type diffusion regions at both sides of said floating gate electrode respectively as a source region and a drain region,
said n-type diffusion region forming said source region having an n−-type diffusion region at the side facing said n-type diffusion region forming said drain region.
Another object of the present invention is to provide a semiconductor integrated circuit having a non-volatile memory cell array, comprising:
a p-type Si substrate;
a plurality of n-type wells formed repeatedly on said Si substrate, each of said n-type wells extending in said Si substrate in a first direction;
a control gate formed of a p-type buried diffusion region, said p-type buried diffusion region being formed in each of said n-type wells so as to extend in said first direction;
a plurality of active regions formed on said Si substrate between a pair of adjacent n-type wells, each of said active regions extending in said first direction and being covered with a tunneling insulation film;
a floating gate electrode provided on each of said n-type wells so as to achieve a capacitance coupling with said p-type buried diffusion region in said n-type well via an insulation film covering said surface of said Si substrate, said floating gate electrode extending over an active region adjacent to n-type well;
n-type diffusion regions formed at both sides of said floating gate electrode in each of said active regions;
a pair of bit lines extending over said Si substrate in a second direction crossing said first direction across said plurality of n-type wells and said

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