Methods of forming a transistor gate

Details Methods of forming a transistor gate Methods of forming a transistor gate

1999-04-23

2003-07-15

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S563000, C438S795000

Reexamination Certificate

active

06593196

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming transistor gates and to transistor constructions.
BACKGROUND OF THE INVENTION
As transistor gate dimensions are reduced and the supply voltage remains constant, the lateral field generated in MOS devices increases. As the electric field becomes strong enough, it gives rise to so-called “hot-carrier” effects in MOS devices. This has become a significant problem in NMOS devices with channel lengths smaller than 1.5 micron, and in PMOS devices with sub-micron channel lengths.
High electric fields cause the electrons in the channel to gain kinetic energy, with their energy distribution being shifted to a much higher value than that of electrons which are in thermal equilibrium within the lattice. The maximum electric field in a MOSFET device occurs near the drain during saturated operation, with the hot electrons thereby becoming hot near the drain edge of the channel. Such hot electrons can cause adverse effects in the device.
First, those electrons that acquire greater than or equal to 1.5 eV of energy can lose it via impact ionization, which generates electron-hole pairs. The total number of electron-hole pairs generated by impact ionization is exponentially dependent on the reciprocal of the electric field. In the extreme, this electron-hole pair generation can lead to a form of avalanche breakdown. Second, the hot holes and electrons can overcome the potential energy barrier between the silicon and the silicon dioxide, thereby causing hot carriers to become injected into the gate oxide. Each of these events brings about its own set of repercussions.
Device performance degradation from hot electron effects have been in the past reduced by a number of techniques. One technique is to reduce the voltage applied to the device, and thus decrease in the electric field. Further, the time the device is under the voltage stress can be shortened, for example, by using a lower duty cycle and clocked logic. Further, the density of trapping sites in the gate oxide can be reduced through the use of special processing techniques. Also, the use of lightly doped drains and other drain engineering design techniques can be utilized.
Further, it has been recognized that fluorine-based oxides can improve hot-carrier immunity by lifetime orders of magnitude. This improvement is understood to mainly be due to the presence of fluorine at the Si/SiO
2
interface reducing the number of strained Si/O bonds, as fewer sites are available for defect formation. Improvements at the Si/SiO
2
interface reduces junction leakage, charge trapping and interface trap generation. However, optimizing the process can be complicated. In addition, electron-trapping and poor leakage characteristics can make such fluorine-doped oxides undesirable and provide a degree of unpredictability in device operation. Use of fluorine across the entire channel length has been reported in, a) K. Ohyu et al., “Improvement of SiO
2
/Si Interface Properties by Fluorine Implantation”; and b) P. J. Wright, et al., “the Effect of Fluorine On Gate Dielectric Properties”.
SUMMARY OF THE INVENTION
In one implementation, a method of forming a transistor includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another aspect, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. The center is preferably substantially void of either fluorine or chlorine. In one implementation, at least one of chlorine or fluorine is angle ion implanted to beneath the edges of the gate. In another, sidewall spacers are formed proximate the opposing lateral edges, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time period effective to diffuse the fluorine or chlorine from the spacers into the gate oxide layer to beneath the gate. Transistors fabricated by such methods, and other methods, are also contemplated.


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