Methods of forming a contact structure in a semiconductor...

Details Methods of forming a contact structure in a semiconductor... Methods of forming a contact structure in a semiconductor...

2001-01-05

2002-07-09

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S773000, C438S783000

Reexamination Certificate

active

06417097

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-50108, filed on Aug. 28, 2000, the contents of which are incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to methods of forming a semiconductor device, and more particularly to methods of forming a contact structure in a semiconductor device.
BACKGROUND OF THE INVENTION
As the integration density of a semiconductor device increases, the width of each wiring line, and the space between the adjacent wiring lines, become smaller and smaller in size. Given these increasing smaller requirements, a self-aligned contact technique has been proposed in order to increase alignment margins during a photolithography process for forming a contact hole.
In a Dynamic Random Access Memory (DRAM) device, a bit line and a storage node are electrically connected to active regions of a semiconductor substrate through self-aligned contact pads. The pads penetrate a predetermined region of an interlayer insulating layer and contact the active regions.
In present methods, an oxide layer containing impurities is widely used as the interlayer insulating layer, since it provides for excellent planarization and electrical insulation. Typically, a BPSG (BoroPhosphoSilicate glass) layer is used as the interlayer insulating layer. The BPSG layer is a silicon oxide layer containing impurities such as boron and phosphorous. The BPSG layer has an excellent reflow characteristic, a low dielectric constant, low stress, and excellent step coverage characteristics as compared to other oxide layer not containing impurities. The BPSG layer is generally reflowed at a temperature of about 850° C. to 1000° C. in order to planarize a top surface thereof.
Despite the advantages of the BPSG layer, there some problems in the contact structure formed in the BPSG layer.
FIGS. 1 and 2
are cross-sectional views of a conventional contact structure using the BPSG layer as an interlayer insulating layer.
Referring to
FIGS. 1 and 2
, a trench isolation layer
3
is formed in a semiconductor substrate
1
to define active regions. A drain region
5
and a source region
7
are formed in the active region. A gate pattern
9
is formed, for example, a word line pattern comprising a gate oxide layer
9
a,
a polysilicon pattern
9
b,
a metal silicide pattern
9
c,
and a capping insulating layer pattern
9
d
which are sequentially stacked. The gate pattern
9
contacts the active regions and bridges the drain region
5
and source region
7
. The gate pattern
9
is then covered with a conformal silicon nitride layer
11
. The silicon nitride layer
11
is then covered with a BPSG layer
13
, filling gap regions between the gate patterns
9
. The BPSG layer
13
and the silicon nitride layer
11
are selectively etched in a self-aligned manner, to form a pad contact hole exposing the drain region
5
. A conductive layer, such as a doped polysilicon layer, is formed in the pad contact hole to form a bit line pad
15
. An insulating layer
17
is formed on the resultant structure having the bit line pad
15
, and the insulating layer
17
is then patterned to form a bit line contact hole
19
exposing the bit line pad
15
. A polycide bit line
21
, a composite layer of a polysilicon layer pattern
21
a
and a metal silicide layer pattern
21
b,
is formed on the insulating layer
17
. The bit line
21
is electrically connected to the bit line pad
15
through the bit line contact hole
19
. At this time, the bit line pad
15
is in contact with the BPSG layer
13
and the drain region
5
. Accordingly, impurities such as phosphorous within the BPSG layer
13
are diffused into the drain region
5
through the bit line pad
15
during subsequent annealing process. As a result, the concentration profile of the drain region
5
is changed, thereby degrading electrical characteristics of the semiconductor device.
In order to solve the above problem, Japanese laid-open patent number 6020989 discloses a method of forming a pad. This method comprises forming a contact hole penetrating a portion of a BPSG layer, forming a silicon oxide spacer on a sidewall of the contact hole, and then forming a conductive pad in the contact hole surrounded by the spacer. However, this method also has some problems associated with sidewall spacer formation. Namely, it is very difficult to form the sidewall spacer in a contact hole having a high aspect ratio. In addition, the active region can be damaged during an etch back process employed while forming the sidewall spacer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of forming a contact structure in a semiconductor device which can prevent impurities in the interlayer insulating layer from being diffused into source/drain region.
In order to achieve the above object and other features of the present invention, a method of forming a contact structure is provided. The method includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole exposing a predetermined portion of the semiconductor substrate. A conductive pad is formed in the pad contact hole. The resultant structure having the conductive pad is subjected to thermal oxidation to form a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.
Preferably, prior to formation of the interlayer insulating layer, a plurality of insulated interconnection patterns, which are parallel to each other, are formed on the semiconductor substrate, and an etch stop layer is formed on the entire surface of the resultant structure having the interconnection patterns. Herein, the plurality of interconnection patterns are formed by sequentially forming an insulating layer, a conductive layer and a capping layer on the semiconductor substrate and sequentially patterning the capping layer and the conductive layer. Accordingly, each of the interconnection patterns comprises an interconnection and a capping layer pattern stacked on the interconnection. The insulating layer can also be patterned. The interconnection may correspond to a word line of a DRAM device.


REFERENCES:
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patent: 5338700 (1994-08-01), Dennison et al.
patent: 5362666 (1994-11-01), Dennison
patent: 5498562 (1996-03-01), Dennison et al.
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patent: 5652164 (1997-07-01), Dennison et al.
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patent: 6261953 (2001-07-01), Uozumi
patent: 6287954 (2001-09-01), Ashley et al.
patent: 6303505 (2001-10-01), Ngo et al.
patent: 6-20989 (1994-01-01), None

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