Methods of fabricating vertical channel field effect...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257SE21014

Reexamination Certificate

active

07459359

ABSTRACT:
A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

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Shengdong Zhang, et al., “Implementation and Characterization of Self-Aligned Double-Gate TFT With Thin Channel and Thick Source/Drain,”IEEE, vol. 49, No. 5, May 2002.
Yang-Kyu Choi et al., “A Spacer Patterning Technology for Nanoscale CMOS,”IEEE, vol. 49, No. 3, Mar. 2002.

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