Methods of fabricating semiconductor devices with barrier...

Details Methods of fabricating semiconductor devices with barrier... Methods of fabricating semiconductor devices with barrier...

2001-05-01

2003-11-04

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S769000, C438S778000

Reexamination Certificate

active

06642095

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and fabricating methods thereof.
2. Background of the Related Art
In semiconductor devices, as CMOS transistors get more highly-integrated, the sizes of NMOS and PMOS transistors become smaller. Thus, device characteristics are deteriorated due to short channels, hot carriers and the like. Therefore, an LDD (lightly doped drain) structure has been utilized for the fabrication of the NMOS/PMOS transistors to improve device characteristics.
When gates of the NMOS and PMOS transistors of CMOS are doped with the same n type impurities, a channel region of the PMOS is not formed at the surface of the substrate but rather, is formed in the bulk, thereby reducing breakdown voltage due to punch-through.
Therefore, dual-gated CMOS transistors consisting of PMOS and NMOS transistors which are heavily doped with p and n type impurities respectively have been developed. The PMOS transistor of the dual-gated CMOS transistor has a channel region at the surface of the substrate, thereby preventing breakdown voltage from being reduced due to punch-through.
When an SiO
2
gate oxide layer is introduced to a PMOS transistor which has a gate electrode made of boron-doped polysilicon, boron ions diffuse into the channel region of a silicon substrate through the gate oxide layer causing the threshold voltage of a completed PMOS transistor to vary.
Accordingly, in the related art, an oxynitride layer consisting of nitrogen piled up at an interface between the gate oxide layer and the silicon substrate formed by annealing in NO (nitric oxide) is used to prevent variations of the threshold voltage in a PMOS transistor due to boron penetration.
FIG. 1A
to
FIG. 1C
show cross-sectional views of forming a gate insulating layer consisting of oxynitride and silicon oxide in a semiconductor device in the related art.
Referring to
FIG. 1A
, a silicon oxide layer
11
for forming a gate insulating layer is formed on a silicon substrate
10
of a semiconductor substrate where a device isolating area and a device active region are defined by a device isolation layer such as a field oxide layer formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation). In this case, the area shown in
FIG. 1A
represents the device active area which may be referred to as a silicon substrate doped with n type impurities or as an n type well.
If the device isolation layer is formed after the formation of the well, a field oxide layer may be formed by LOCOS or STI at the junction between n and p type wells for electrical device isolation. Additionally, ion implantation is carried out for adjusting threshold voltage of a PMOS device in the exposed silicon substrate
10
before the formation of a silicon oxide layer.
Referring to
FIG. 1B
, nitric oxide (hereinafter abbreviated NO) annealing is carried out on the exposed silicon oxide layer
11
. As a result of the NO annealing, an oxynitride layer
12
is formed consisting of nitrogen piled up at an interface between the silicon substrate
10
and the silicon oxide layer
11
. The oxynitride layer
12
, as well as, the silicon oxide layer
11
in part become a gate insulating layer for a MOS transistor. Thus, the oxynitride layer
12
provides traps at the interface, and the traps in turn reduce transconductance of the gate insulating layer.
Referring to
FIG. 1C
, a polysilicon layer
13
doped with p type impurities such as boron and the like is formed on the exposed silicon oxide layer
11
by chemical vapor deposition (hereinafter abbreviated CVD). After, a gate electrode is formed by patterning the doped polysilicon layer
13
, the silicon oxide layer
11
, and the oxynitride layer
12
by photolithography. A PMOS transistor is completed by forming p type impurity diffusion regions doped with B, BF
2
or the like in the substrate centering around the gate electrode.
Unfortunately, in the related art, oxynitride is formed only at an interface between the silicon oxide layer and the silicon substrate, thereby only somewhat reducing transconductance of the gate insulating layer due to reciprocal interaction among traps generated from oxynitride. Moreover, the related art reduces device reliability due to a threshold voltage shift caused by failing to prevent boron penetration into the channel region because boron ions still diffuse into the gate oxide layer despite the formation of the oxynitride layer between the silicon oxide layer and the silicon substrate.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the invention is to improve device characteristics such as a threshold voltage and the like.
Another object of the present invention is to prevent impurities from penetrating into a channel region.
A further object of the present invention is to prevent transconductance.
A further object of the present invention is to prevent problems caused by reciprocal reaction of traps from decreasing by re-oxidation.
The object of the present invention is to provide a gate insulating layer of a PMOS device which improves device characteristics such as threshold voltage and the like by preventing p type impurities from penetrating into a channel region of a substrate through an SiO
2
layer as well as preventing transconductance due to reciprocal interaction of traps, wherein a first and a second oxynitride layer are formed at a first interface between a SiO
2
layer and a gate of p-doped polysilicon and a second interface between the SiO
2
layer and a silicon substrate, respectively.
Another object of the present invention is to provide a method of forming a gate insulating layer of a PMOS device which improves device characteristics such as threshold voltage and the like by preventing p type impurities from penetrating into a channel region of a substrate through a SiO
2
layer as well as preventing transconductance due to reciprocal interaction of traps, wherein a silicon nitride layer is formed on a undoped polysilicon layer and wherein a first and a second oxynitride layer are formed at a first interface between a SiO
2
layer and a gate of p-doped polysilicon and a second interface between the SiO
2
layer and a silicon substrate, respectively.
Another object of the present invention is to provide a PMOS transistor including a gate electrode and impurity diffusion region which improves device characteristics such as threshold voltage and the like by providing a gate insulating layer consisting of oxynitride/silicon oxide/oxynitride to prevent boron penetration into a substrate and by removing traps existing in oxynitride by re-oxidation to improve transconductance of the gate insulating layer.
A further object of the present invention is to provide a method of fabricating a PMOS transistor which improves device characteristics such as threshold voltage and the like by preventing p type impurities from penetrating into a channel region of a substrate through an SiO
2
layer as well as preventing transconductance due to reciprocal interaction of traps from decreasing by re-oxidation, wherein the PMOS transistor is fabricated by forming a first oxynitride layer, an SiO
2
layer, a second oxynitride layer, a polysilicon layer and a nitride layer, by patterning the above layers to form a gate electrode and a gate insulating layer and by forming source and drain regions.
As a device becomes more highly integrated, the size of the device is reduced, thus leading to the gate insulating layer of the device becoming thinner. In a PMOS transistor having such a thin gate insulating layer, boron as a dopant for a gate electrode can then penetrate into the gate insulating layer and further into a channel region of a substrate to change the threshold vo

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