Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-12-25
2007-12-25
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S637000, C438S197000, C438S198000, C438S199000, C257SE51005, C257SE29119, C257SE29004
Reexamination Certificate
active
11098648
ABSTRACT:
Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.
REFERENCES:
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 6022766 (2000-02-01), Chen et al.
patent: 6525340 (2003-02-01), Colavito et al.
patent: 6653714 (2003-11-01), Matsuno et al.
patent: 2001/0023953 (2001-09-01), Schuegraf et al.
patent: 2002/0119624 (2002-08-01), Schuegraf et al.
patent: 2002/0197794 (2002-12-01), Lee
patent: 10-027887 (1998-01-01), None
patent: 11-233789 (1999-08-01), None
patent: 10-2003-0002745 (2003-01-01), None
Cho Won-Seok
Han Myang-Sik
Hwang Byung-Jun
Jang Jae-Hoon
Jung Soon-Moon
Le Thao P.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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